ARM应用笔记179：Cortex-M3嵌入式软件开发

Copyright©2007.Allrightsreserved.ARMDAI0179BApplicationNote179Cortex™-M3EmbeddedSoftwareDevelopmentReleasedon:March2007ApplicationNote1792Copyright©2007.Allrightsreserved.ARMDAI0179BApplicationNote179Cortex-M3EmbeddedSoftwareDevelopmentCopyright©2007.Allrightsreserved.ReleaseInformationProprietaryNoticeWordsandlogosmarkedwith®or™areregisteredtrademarksortrademarksofARMLimitedintheEUandothercountries,exceptasotherwisestatedbelowinthisproprietarynotice.Otherbrandsandnamesmentionedhereinmaybethetrademarksoftheirrespectiveowners.Neitherthewholenoranypartoftheinformationcontainedin,ortheproductdescribedin,thisdocumentmaybeadaptedorreproducedinanymaterialformexceptwiththepriorwrittenpermissionofthecopyrightholder.Theproductdescribedinthisdocumentissubjecttocontinuousdevelopmentsandimprovements.AllparticularsoftheproductanditsusecontainedinthisdocumentaregivenbyARMingoodfaith.However,allwarrantiesimpliedorexpressed,includingbutnotlimitedtoimpliedwarrantiesofmerchantability,orfitnessforpurpose,areexcluded.Thisdocumentisintendedonlytoassistthereaderintheuseoftheproduct.ARMLimitedshallnotbeliableforanylossordamagearisingfromtheuseofanyinformationinthisdocument,oranyerrororomissioninsuchinformation,oranyincorrectuseoftheproduct.WherethetermARMisuseditmeans“ARMoranyofitssubsidiaries”asappropriate.ConfidentialityStatusThisdocumentisNon-Confidential.Therighttouse,copyanddisclosethisdocumentmaybesubjecttolicenserestrictionsinaccordancewiththetermsoftheagreemententeredintobyARMandthepartythatARMdeliveredthisdocumentto.ProductStatusTheinformationinthisdocumentisfinal,thatisforadevelopedproduct.WebAddress(withdrawn)March2007BSecondreleaseApplicationNote179ARMDAI0179BCopyright©2007.Allrightsreserved.31TheCortex™-M3ThisapplicationnoteintroducesthemainfeaturesoftheARMCortex™-M3processoranddescribesdifferentaspectsofdevelopingsoftwareforit.ItalsocoversthemigrationofexistingARMprojectstotheCortex-M3platform.TheARMCortex-M3isahighperformance,lowcostandlowpower32-bitRISCprocessor.TheCortex-M3processoronlyexecutesThumb-2instructions.ItdoesnotsupporttheARMinstructionset.TheCortex-M3processorisbasedontheARMarchitecturev7-MandhasanefficientHarvard3-stagepipelinecore.Italsofeatureshardwaredivideandlow-latencyInterruptServiceRoutine(ISR)entryandexit.AswellastheCPUcore,theCortex-M3processorincludesanumberofothercomponents.TheseincludeaNestedVectoredInterruptController(NVIC),anoptionalMemoryProtectionUnit(MPU),Timer,DebugAccessPort(DAP)andoptionalEmbeddedTraceMacrocell(ETM).TheCortex-M3alsohasafixedmemorymap.1.1NestedVectoredInterruptController(NVIC)Dependingontheimplementationusedbythesiliconmanufacturer,theNVICcansupportupto240externalinterruptswithupto256differentprioritylevelsthatcanbedynamicallyreprioritized.Itsupportsbothlevelandpulseinterruptsources.Theprocessorstateisautomaticallysavedbyhardwareoninterruptentryandisrestoredoninterruptexit.TheNVICalsosupportstail-chainingofinterrupts.TheuseofanNVICintheCortex-M3meansthatthevectortableforaCortex-M3isverydifferenttopreviousARMcores.TheCortex-M3vectortablecontainstheaddressoftheexceptionhandlersandISR,notinstructionsasmostotherARMcoresdo.Theinitialstackpointerandtheaddressoftheresethandlermustbelocatedat0x0and0x4respectively.ThesevaluesarethenloadedintotheappropriateCPUregistersatreset.1.2MemoryProtectionUnit(MPU)TheMPUisanoptionalcomponentoftheCortex-M3.Ifincluded,itprovidessupportforprotectingregionsofmemorythroughenforcingprivilegeandaccessrules.Itsupportsuptoeightdifferentregions,eachofwhichcanbesplitintoafurthereightequal-sizesub-regions.1.3DebugAccessPort(DAP)TheDAPusesanAHB-APinterfacetocommunicatewiththeprocessorandotherperipherals.TherearetwodifferentsupportedimplementationsoftheDebugPort,theSerialWireJTAGDebugPort(SWJ-DP)andtheSerialWireDebugPort(SW-DP).YourCortex-M3implementationmightcontaineitherofthesedependingontheimplementationusedbyyoursiliconmanufacturer.1.4MemorymapUnlikemostpreviousARMcores,theoveralllayoutofthememorymapofadevicebasedaroundtheCortex-M3isfixed.ThisallowseasyportingofsoftwarebetweendifferentsystemsbasedontheCortex-M3.Theaddressspaceissplitintoanumberofdifferentsections.ThisisshowninFigure1onpage4anddescribedinTable2onpage4.ApplicationNote1794Copyright©2007.Allrightsreserved.ARMDAI0179BFigure1Cortex-M3memorymapTable2DetailsofCortex-M3memorymapMemoryRegionDescriptionAccessedviabuscodeForcodememory(flash,ROM,orremappedRAM).ICodeandDCodeSRAMForon-chipSRAMwithbit-bandingfeature.systemperipheralFornormalperipheralswithbit-bandingfeature.systemexternalRAMForexternalmemory.system9HQGRUVSHFLILF3ULYDWHSHULSKHUDOEXVH[WHUQDO3ULYDWHSHULSKHUDOEXVLQWHUQDO%LWEDQGLQJ([WHUQDOGHYLFH*%([WHUQDO5$0*%3HULSKHUDO65$0&RGH*%*%*%':7)3%5HVHUYHG,705HVHUYHG73,8(70520WDEOH([WHUQDO33%%LWEDQGLQJ%LWEDQGDOLDV%LWEDQGDOLDV0%0%0%0%0%0%[()))))[())[([([([())))[()[(([([([([(6\VWHPFRQWUROVSDF