亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计

27520065CHINESEJOURNALOFSEMICONDUCTORSVol.27No.5May,2006­Correspondingauthor.Email:[e-mail]8December2005,revisedmanuscriptreceived7January2006Z2006ChineseInstituteofElectronicsDesigningLeakage2TolerantandNoise2ImmuneEnhancedLowPowerWideORDominosinSub270nmCMOSTechnologiesGuoBaozeng1,GongNa1,­,andWangJinhui2(1CollegeofElectronicandInformationEngineering,HebeiUniversity,Baoding071002,China)(2LaboratoryofVLSI&Systems,CollegeofElectronicInformation&ControlEngineering,BeijingUniversityofTechnology,Beijing100022,China)Abstract:Twonewcircuittechniquestosuppressleakagecurrentsandenhancenoiseimmunitywhiledecreasingtheactivepowerareproposed.Eight2inputORgatecircuitsconstructedwiththesetechniquesaresimulatedusing45nmBSIM4SPICEmodelsinHSPICE.Thesimulationresultsshowthattheproposedcircuitseffectivelylowertheactivepower,reducethetotalleakagecurrent,andenhancespeedundersimilarnoiseimmunityconditions.Theactivepowerofthetwoproposedcircuitscanbereducedbyupto818%and1118%whileenhancingthespeedby915%and1317%ascomparedtodualVtdominoORgateswithnogatingstage.Atthesametime,thetotalleakagecurrentsarealsoreducedbyupto8018%and8214%,respectively.Basedonthesimulationresults,thestateoftheevalu2ationnodeisalsodiscussedtoreducethetotalleakagecurrentsofdualVtdominos.Keywords:lowpower;leakagecurrent;ORdominos;noiseimmunityEEACC:1130B;1265CLCnumber:TN4Documentcode:AArticleID:025324177(2006)05208042081IntroductionWideORdominosorsimilarstructuresarecommonlyemployedinregisterandcachearraybitlinedesign[1].Astechnologyisscalingdown,sup2plyvoltagesmustbereducedtokeepdynamicpow2eratacceptablelevels[2,3].Atthesametime,thethresholdvoltage(Vt)andgateoxidethickness(tox)oftransistorsmustbereducedtoaccompanythereductionofthesupplyvoltagetomeetper2formancerequirements.However,thesub2thresh2oldleakageandgateleakagecurrentsincreaseex2ponentiallywiththescalingofVtandtox.Worstofall,duringthesleepmode,whenthecircuitsarenotoperating,leakagecurrentsstilloccur.The2001InternationalTechnologyRoadmapforSemicon2ductors(ITRS)[4]predictedthatbythe70nmgen2eration,leakagemayconstituteasmuchas50per2centofthetotalpowerconsumption.Atthesametime,theincreasingofsub2thresholdleakagecur2rentsandgateleakagecurrentswiththescalingoftechnologyalsodegradesthenoiseimmunityofwideORdominogates,andtheerror2freeoperationofdominoshasbecomeamajorchallenge[5].Therefore,thereisaneedtofindawaytore2duceleakagecurrentsandimprovecircuitrobust2nesswhiledecreasingtheactivepower.Priorcir2cuit2levelapproachestoleakagepowerreductionandperformanceenhancementinclude:body2biascontrol[6],inputvectorcontrol[7],sleeptran2sistors[8],variablethreshold2voltageCMOStech2nique(VTCMOS)[9],andvariablesupplyvoltagestechnique(VS)[10].Architecture2levelleakagepowerreductiontechniqueshavefocusedprimarilyonSRAMS[11,12].Eachtechniquehasitsshareofstrengthsandweaknesses,andinthispaperwefo2cusontheformer.WeproposetwonewwideORdominocircuittechniquesandstudytheirimpactonthefollowingdesignparameters:thesub2thresholdleakagecurrent,gateleakagecurrent,activepower,delaytime,DCrobustness,andACnoisemargins.2ProposedwideORdominosAsdescribedinSec.1,leakagecurrentshavebecomeanimportantissuethreateningtheper2formanceofdominocircuits,especiallyforwideORdominos.Bothsub2thresholdleakageandgateleak2agecurrentsincreaseexponentiallywiththescalingofVtandtox,asshowninFig.1(a).Atthesame5GuoBaozengetal.:DesigningLeakage2TolerantandNoise2ImmuneEnhancedLowPowerWidetime,therisingleakagecurrentsdegeneratetheperformanceofthecircuits,eventuallyleadingtofailure[5].Figure1(b)showsthenormalizedDCro2bustnessandACnoisemarginsofseveraldifferentfin2inORgatesin45nmand65nmCMOStechnol2ogy.Obviously,boththeDCrobustnessandACnoisemarginsdegradewiththescalingoftechnolo2gyandtheincreasingoffan2innumber.Fig.1(a)Comparisonofthesub2thresholdleakageandgateleakagecurrentsproducedbyannMOStransistorforvarioussupplyvoltageSub2thresholdleakagecurrentatVgs=0andVds=Vdd;GateleakagecurrentatVgs=Vgd=Vgb=Vdd;(b)ComparisonoftheDCrobustnessandACnoisemarginsofseveraldifferentfin2inORgatesin45nmand65nmtechnologyTheDCrobustnessandACnoisemarginsarenormalizedtothoseof22inputORdominosin65nmtechnology,respectively.Tosuppressthesub2thresholdleakagecur2rent,whichincreaseswiththescalingofVt,thedu2alVttechniquewasproposedinRef.[13].ThetechniqueoptimizedthecircuitspeedandleakagecurrentsbyusinglowVtandhighVttransistorsonthetimingcriticalpathsandnon2criticalpaths,re2spectively[seeFig.2(b)].Withthistechnique,itisnecessarytogatealltheinitialinputsofthedomi2nogatestoplacethesleepdominogatesintoalowsub2thresholdleakagestate[13,14].Fig.2N2inputORdominogates(a)StandardORdominos;(b)DualVtORdominosThehighVttransistorsaresymbolicallyrepresentedbyathicklineinthechannelregion.Obviously,thedualVttechniquedoesnottaketheeffectofthegateleakagecurrentintoaccount.Wheninputsaregatedandtheevaluationnodeisdischarged,thesub2thresholdleakagecurrentisminimized.However,thegateleakagecurrentisfastbecominganon2negligiblecomponentastoxis50827gettingthinner.EspeciallyinwideORdominos,thepull2downnMOSnetwo