Verilog的135个经典设计实例

【19~3.1】4位全加器王金明：《VerilogHDL程序设计教程》m。duleadder4(cout,sum,ina,inb,cin);。utput[3:0]sum;。utputcout;input[3:0]ina,inb;inputcin;assign{cout,sum}=ina+inb+cin;endm。dule【例3.2】4位计数器m。dulecount4(out,reset,clk);。utput[3:0］。ut;inputreset,clk;reg[3:0]out;always@(p。sedgeelk)beginif(reset)out=O;elseout=out+l;endendm。dule【19~3.3】4位全加器的仿真程序、timescalelns/lns、include”adder4.v”.,PJ.,rbe’da‘αa1Jnue:13ufLdq。emxregcin;wire[3:0]sum;wirecout;integeri,j;／／同步复位／／计数／／测试模块的名字／／测试输入信号定义为reg型／／测试输出信号定义为wire型always#5cin=~cin;adder4adder(sum,cout,a,b,cin);／／调用测试对象／／设定cin的取值initialbegina=O;b=O;cin=O;f。r(i=l;i16;i=i+l)#10a=i;end／／设定a的取值-1-程序文本initiall+·「Id--·「Jrb咱i-1J气」UF=LAn--i(qzoe。14hUSE－A甘／／设定b的取值endinitial／／定义结果显示格式begin♀monitor($time，，，”毛d＋毛d＋毛b＝｛告b，毛d｝”，a,b,cin,cout,sum);#160$finish;endendm。dule【19~3.4]4位计数器的仿真程序、timescalelns/lns、include”count4.v”.,pt;一t4ensueorc’bhellcudq。emx／／测试输入信号定义为reg型／／测试输出信号定义为wire型wire[3:0]out;parameterDELY=lOO;count4mycount(out,reset,clk);／／调用测试对象always#(DELY/2)elk=~elk;／／产生时钟波形initialbegin／／激励信号定义#DELY#DELYelk=0;reset=O;reset=l;reset=O;#(DELY女20)$finish;end／／定义结果显示格式initial$monitor($time，，，”elk＝毛dreset＝屯dout＝毛d”，elk,reset,out);endm。dule【侣。3.5】“与－或－非”门电路。utputF;／／模块名为AOI（端口歹lj表A,B,C,D,F)／／模块的输入端口为A,B,C,D／／模块的输出端口为Fm。duleAOI(A,B,C,D,F);inputA,B,C,D;-2-王金明：《VerilogHDL程序设计教程》wireA,B,C,D,F;／／定义信号的数据类型assignF=~((A&B)I(C&D));／／逻辑功能描述endm。dule【19~5.1】用case语旬描述的4选1数据选择器m。dulemux4_l(out,in0,inl,in2,in3,sel);。utputout;inputin0,inl,in2,in3;input[l:O]sel;regout;always@(inO。zinl。zin2。zin3。zsel)case(sel)2’bOO:out=inO;2’bOl:out=inl;2’blO:out=i口2;2’bll:out=in3;default:out=2’bx;endcaseendm。dule【19~5.2】同步置数、同步清零的计数器m。dulecount(out,data,load,reset,clk);。utput[7:0]out;input[7:0]data;inputload,clk,reset;reg[7:OJout;always@(p。sedgeelk)beginif(!reset)out=8’hOO;elseif(load)out=data;elseout=out+1;endendm。dule／／敏感信号列表//elk上升沿触发／／同步清0，低电平有效／／同步预置／／计数【19~5.3】用always过程语旬描述的简单算术逻辑单元、defineadd3’dO、defineminus3’dl、defineband3’d2、definebor3’d3、definebnot3’d4-3-程序文本m。dulealu(out,opcode,a,b);。utput[7:0]out;reg[7:0]out;input[2:0]opcode;input[7:0]a,b;always@(opcode。xa。zb)begincase(opcode)、add:out=a+b;、minus:out=a-b;、band:out=a&b;、bor:out=alb;、bnot:out＝呻a;default:out=8’hx;endcaseendendm。dule／／操作码／／操作数／／电平敏感的always块／／加操作／／减操作／／求与／／求或／／求反／／未收到指令时，输出任意态【19~5.4】用initial过程语旬对测试变量A、B、C赋值、timescalelns/lnsm。duletest;regA,B,C;initialbeginA=O;B=l;C=O;#50A=l;B=O;#50A=O;c=l;#50B=l;#50B=O;C=O;#50$finishendendmodule、timescalelOns/lns【例5.5】用be伊1-end串行块产生信号波形m。dulewavel;regwave;nu－－牛--e、4cycre＆』咽·－eam--atz-lanpibegin-4-王金明：《VerilogHDL程序设计教程》wave=O;#(cycle/2)wave=l;#(cycle/2)wave=O;#(cycle/2)wave=l;#(cycle/2)wave=O;#(cycle/2)wave=l;#(cycle/2)$finishendinitial$monitor｛♀time，，，”wave＝告b”，wave);endm。dule自【19~5.6】用fork才oin并行块产生信号波形、timescalelOns/lnsm。dulewave2;regwave;.,RJ=e14CV4cze＋』唱·－eam-Latr·-anpif。rkwave=O;#(cycle)wave=l;#(2*cycle)wave=O;#(3*cycle)wave=l;#(4*cycle)wave=O;#(S*cycle)wave=l;#(6*cycle)$finish;3。ininitial$monitor($time，，，”wave＝每b”，wave);endm。dule【例5.7】持续赋值方式定义的2选l多路选择器m。duleMUX21_1(out,a,b,sel);inputa,b,sel;。utputout;assignout=(sel==O)?a:b;／／持续赋值，如果sel为0，贝I]out=a：否则out=bendmodule【19~5.8】阻塞赋值方式定义的2选l多路选择器m。duleMUX21_2(out,a,b,sel);inputa,b,sel;-5-程序文本。utputout;regout;always@(a。zb。zsel)beginif(sel==O)out=a;／／阻塞赋值elseout=b;endendmodule【侣。5.9】非阻塞赋值m。dulenon_block(c,b,a,clk);。utputc,b;inputclk,a;regc,b;always@(p。sedgeelk)beginb=a;c=b;endendm。dule【19~5.10】阻塞赋值m。duleblock(c,b,a,clk);。utputc,b;inputclk,a;regc,b;always@(p。sedgeelk)begine问L的d．U==ndbce。·伽ne【侣。5.11】模为60的BCD码加法计数器m。dulecount60(qout,cout,data,load,cin,reset,clk);。utput[7:0]qout;。utputcout;input[7:0]data;inputload,cin,clk,reset;reg[7:0]qout;always@(p。sedgeelk)//elk上升沿时刻计数-6-王金明：《VerilogHDL程序设计教程》beginif(reset)elseif(load)elseif(cin)beginqout=O;qout=data;／／同步复位／／同步置数if(qout[3:0]==9)／／低位是否为9，是则beginqout[3:0]=0;／／囡0，并判断高位是否为5if(qout[7:4]==5)qout[7:4]=0;elseqout[7:4]=qout[7:4]+1;endelseqout[3:0]=qout[3:0]+1;endendassigncout=((qout==8’h59)&cin)?l:O;endm。dule【例5.12】BCD码一七段数码管显示译码器m。duledecode4_7(decodeout,indec);。utput[6:0]decodeout;input[3:0]indec;reg[6:0]decodeout;always@(indec)begincase(indec)4’dO:decodeout=7’bllllllO;4’dl:decodeout=7’bOllOOOO;4’d2:decodeout=7’b1101101;4’d3:decodeout=7’bllllOOl;4’d4:decodeout=7’b0110011;4’d5:decodeout=7’b1011011;4’d6:decodeout=7’blOlllll;4’d7:decodeout=7’blllOOOO;4’d8:decodeout=7’blllllll;4’d9:decodeout=7’bllllOll;default:decodeout=7’bx;endcaseend／／高位不为5，则加l／／低位不为9，则加l／／产生进位输出信号／／用case语句进行译码-7-程序文本-8-endm。dule【侣。5.13】用casez描述的数据选择器m。dulemux_casez(out,a,b,c,d,select);。utputout;inputa,b,c,d;input[3:0]select;regout;always@(select。za。zb。zc。zd)begincasez(select)end4’b???l:out=a;4’b??l?:out=b;4’b?l??:out=c;4’bl???:out=d;endcaseendm。dule【例5.14】隐含锁存器举例m。duleburied_ff(c,b,a);。utputc;inputb,a;regc;always@(aorb)beginif((b==l)&&(a==l))c=a&b;endendm。dule【19~5.15】用for语旬描述的七人投票表决器m。dulevoter7(pass,vote);。utputpass;input[6:0]vote;reg[2:0]sum;integeri;regpass;always@(vote)beginsum=O;f。r(i=O;i=6;i=i+l)if(vote[i])sum=sum+l;if(sum[2])pass=l;王金明：《VerilogHDL程序设计教程》//for语旬／／若超过