zynq-axi_dma--linux

转自：Lauri'sblog网址：:MM2S(memory-mappedtostream)transportsdatafromDDRmemorytoFPGAandS2MM(streamtomemory-mapped)transportsarbitrarydatastreamtoDDRmemory.AXIDMAinternalsMinimalworkinghardwareThesimplestwaytoinstantiateAXIDMAonZynq-7000basedboardsistotakeboardvendor'sbasedesign,stripunnecessarycomponents,addAXIDirectMemoryAccessIP-coreandconnecttheoutputstreamporttoit'sinputstreamport.ThisessentiallyimplementsmemcpyfunctionalitywhichcanbetriggeredfromARMcorebutoffloadedtoprogrammablefabric.AXIDirectMemoryAccessstreamoutputisloopedbacktostreaminputTobemoreprecise,followingisthecorrespondinghighlevelblockdesign.Highspeedclocklineishighlightedinyellowasitrunsonhigherfrequencyof150MHzwhilethegeneralpurposeportrunsat100MHz.Clockdomainerrorscanusuallybetrackedbacktoconflictingclocklines.Thisisfurtherexplainedintheendofthisarticle.HighlevelblockdesigncorrespondingtoabstractdesignpresentedearlierIntheAXIDirectMemoryAccessIP-corecustomizationdialogreadchannelandwritechannelcorrespondrespectivelytoMM2SandS2MMportionsoftheDMAblock.Memorymapdatawidthof32bitsmeansthat4byteswillbetransferredduringonebuscycle.Thismeansthetdataportofthestreaminterfacewillbe32bitswide.Bothread/writechannelsareenabledandscatter-gatherengineisdisabledAXIDirectMemoryAccesscomponent'scontrolregister,statusregisterandtransferaddressregistersareaccessibleviatheAXILiteslaveportwhichismemorymappedtoaddressrangeof0x40400000-0x4040FFFF.Thewholememoryrangeof0x00000000-0x1FFFFFFFisaccessibleviabothstreamtomemory-mappedandmemory-mappedtostreamchannel.AXIDMA[1]documentationhastheoffsetsoftheregistersaccessibleviaAXILiteport.InthiscaseMM2Scontrolregisterof32-bitsisaccessibleat0x40400000,MM2Sstatusregisterof32-bitsat0x40400004andsoforth.NotethatcustomizingtheAXIDirectMemoryAccessIP-coreparameterscausesmemoryrangestoberesetunderAddressEditor!MinimalworkingsoftwareWhenitcomestowritingCcodeIseealarmingtendencyofdefaultingtovendorprovidedcomponents:stand-alonebinarycompilers,Linuxdistributions,boardsupportpackages,wrapperswhileavoidinglearningwhatactuallyhappensinthehardware/software.AsdescribedinmyearlierarticlephysicalmemorycanbeaccessedinLinuxvia/dev/memblockdevice.ThismakesitpossibletoaccessAXILiteregisterssimplybyreading/writingtoamemorymappedrangefrom/dev/mem.TouseDMAcomponentminimallyfourstepshavetobetaken:1.StarttheDMAchannel(MM2S,S2MMorboth)bywriting1tocontrolregister2.Writestart/destinationaddressestocorrespondingregisters3.Toinitiatethetransfer(s)writetransferlength(s)tocorrespondingregister(s).4.MonitorstatusregisterforIOC_Irqflag.Inthiscasewe'recopying32bytesfromphysicaladdressof0x0E000000tophysicaladdresof0x0F000000.Notethatkernelmayallocatememoryforotherprocessesinthatrangeandthatistheprimaryreasontowriteakernelmodulewhichwouldrequest_mem_regionsonootherprocesseswouldoverlapwiththememoryrange.Besidesreservingmemoryrangesthekernelmoduleprovidesasanitizedwayofaccessingthehardwarefromuserspaceapplicationsvia/dev/blahblockdevices.linux上的程序：/***ProofofconceptoffloadedmemcopyusingAXIDirectMemoryAccessv7.1*/#includestdio.h#includeunistd.h#includefcntl.h#includetermios.h#includesys/mman.h#defineMM2S_CONTROL_REGISTER0x00#defineMM2S_STATUS_REGISTER0x04#defineMM2S_START_ADDRESS0x18#defineMM2S_LENGTH0x28#defineS2MM_CONTROL_REGISTER0x30#defineS2MM_STATUS_REGISTER0x34#defineS2MM_DESTINATION_ADDRESS0x48#defineS2MM_LENGTH0x58unsignedintdma_set(unsignedint*dma_virtual_address,intoffset,unsignedintvalue){dma_virtual_address[offset2]=value;}unsignedintdma_get(unsignedint*dma_virtual_address,intoffset){returndma_virtual_address[offset2];}intdma_mm2s_sync(unsignedint*dma_virtual_address){unsignedintmm2s_status=dma_get(dma_virtual_address,MM2S_STATUS_REGISTER);while(!(mm2s_status&112)||!(mm2s_status&11)){dma_s2mm_status(dma_virtual_address);dma_mm2s_status(dma_virtual_address);mm2s_status=dma_get(dma_virtual_address,MM2S_STATUS_REGISTER);}}intdma_s2mm_sync(unsignedint*dma_virtual_address){unsignedints2mm_status=dma_get(dma_virtual_address,S2MM_STATUS_REGISTER);while(!(s2mm_status&112)||!(s2mm_status&11)){dma_s2mm_status(dma_virtua