XCF02S中文资料

DS123(v2.9)May09,2006©2003-2006Xilinx,Inc.Allrightsreserved.AllXilinxtrademarks,registeredtrademarks,patents,anddisclaimersareaslistedat•In-SystemProgrammablePROMsforConfigurationofXilinxFPGAs•Low-PowerAdvancedCMOSNORFLASHProcess•Enduranceof20,000Program/EraseCycles•OperationoverFullIndustrialTemperatureRange(–40°Cto+85°C)•IEEEStandard1149.1/1532Boundary-Scan(JTAG)SupportforProgramming,Prototyping,andTesting•JTAGCommandInitiationofStandardFPGAConfiguration•CascadableforStoringLongerorMultipleBitstreams•DedicatedBoundary-Scan(JTAG)I/OPowerSupply(VCCJ)•I/OPinsCompatiblewithVoltageLevelsRangingFrom1.5Vto3.3V•DesignSupportUsingtheXilinxAllianceISEandFoundationISESeriesSoftwarePackages•XCF01S/XCF02S/XCF04S♦3.3Vsupplyvoltage♦SerialFPGAconfigurationinterface(upto33MHz)♦Availableinsmall-footprintVO20andVOG20packages.•XCF08P/XCF16P/XCF32P♦1.8Vsupplyvoltage♦SerialorparallelFPGAconfigurationinterface(upto33MHz)♦Availableinsmall-footprintVO48,VOG48,FS48,andFSG48packages♦Designrevisiontechnologyenablesstoringandaccessingmultipledesignrevisionsforconfiguration♦Built-indatadecompressorcompatiblewithXilinxadvancedcompressiontechnologyDescriptionXilinxintroducesthePlatformFlashseriesofin-systemprogrammableconfigurationPROMs.Availablein1to32Megabit(Mbit)densities,thesePROMsprovideaneasy-to-use,cost-effective,andreprogrammablemethodforstoringlargeXilinxFPGAconfigurationbitstreams.ThePlatformFlashPROMseriesincludesboththe3.3VXCFxxSPROMandthe1.8VXCFxxPPROM.TheXCFxxSversionincludes4-Mbit,2-Mbit,and1-MbitPROMsthatsupportMasterSerialandSlaveSerialFPGAconfigurationmodes(Figure1,page2).TheXCFxxPversionincludes32-Mbit,16-Mbit,and8-MbitPROMsthatsupportMasterSerial,SlaveSerial,MasterSelectMAP,andSlaveSelectMAPFPGAconfigurationmodes(Figure2,page2).AsummaryofthePlatformFlashPROMfamilymembersandsupportedfeaturesisshowninTable1.BLBluePlatformFlashIn-SystemProgrammableConfigurationPROMSDS123(v2.9)May09,20060ProductSpecificationRTable1:PlatformFlashPROMFeaturesDeviceDensityVCCINTVCCORangeVCCJRangePackagesProgramIn-systemviaJTAGSerialConfig.ParallelConfig.DesignRevisioningCompressionXCF01S1Mbit3.3V1.8V–3.3V2.5V–3.3VVO20/VOG20✓✓XCF02S2Mbit3.3V1.8V–3.3V2.5V–3.3VVO20/VOG20✓✓XCF04S4Mbit3.3V1.8V–3.3V2.5V–3.3VVO20/VOG20✓✓XCF08P8Mbit1.8V1.5V–3.3V2.5V–3.3VVO48/VOG48FS48/FSG48✓✓✓✓✓XCF16P16Mbit1.8V1.5V–3.3V2.5V–3.3VVO48/VOG48FS48/FSG48✓✓✓✓✓XCF32P32Mbit1.8V1.5V–3.3V2.5V–3.3VVO48/VOG48FS48/FSG48✓✓✓✓✓PlatformFlashIn-SystemProgrammableConfigurationPROMSDS123(v2.9)May09,2006(D0)pinthatisconnectedtotheFPGADINpin.Newdataisavailableashortaccesstimeaftereachrisingclockedge.TheFPGAgeneratestheappropriatenumberofclockpulsestocompletetheconfiguration.WhentheFPGAisinSlaveSerialmode,thePROMandtheFPGAarebothclockedbyanexternalclocksource,oroptionally,fortheXCFxxPPROMonly,thePROMcanbeusedtodrivetheFPGA’sconfigurationclock.TheXCFxxPversionofthePlatformFlashPROMalsosupportsMasterSelectMAPandSlaveSelectMAP(orSlaveParallel)FPGAconfigurationmodes.WhentheFPGAisinMasterSelectMAPmode,theFPGAgeneratesaconfigurationclockthatdrivesthePROM.WhentheFPGAisinSlaveSelectMAPMode,eitheranexternaloscillatorgeneratestheconfigurationclockthatdrivesthePROMandtheFPGA,oroptionally,theXCFxxPPROMcanbeusedtodrivetheFPGA’sconfigurationclock.WithBUSYLowandCFHigh,afterCEandOEareenabled,dataisavailableonthePROMsDATA(D0-D7)pins.Newdataisavailableashortaccesstimeaftereachrisingclockedge.ThedataisclockedintotheFPGAonthefollowingrisingedgeoftheCCLK.Afree-runningoscillatorcanbeusedintheSlaveParallel/SlaveSelecMAPmode.TheXCFxxPversionofthePlatformFlashPROMprovidesadditionaladvancedfeatures.Abuilt-indatadecompressorsupportsutilizingcompressedPROMfiles,anddesignrevisioningallowsmultipledesignrevisionstobestoredonasinglePROMorstoredacrossseveralPROMs.Fordesignrevisioning,externalpinsorinternalcontrolbitsareusedtoselecttheactivedesignrevision.MultiplePlatformFlashPROMdevicescanbecascadedtosupportthelargerconfigurationfilesrequiredwhentargetinglargerFPGAdevicesortargetingmultipleFPGAsdaisychainedtogether.WhenutilizingtheadvancedfeaturesfortheXCFxxPPlatformFlashPROM,suchasdesignrevisioning,programmingfileswhichspancascadedPROMdevicescanonlybecreatedforcascadedchainscontainingonlyXCFxxPPROMs.IftheadvancedXCFxxPfeaturesarenotenabled,thenthecascadedchaincanincludebothXCFxxPandXCFxxSPROMs.Figure1:XCFxxSPlatformFlashPROMBlockDiagramControlandJTAGInterfaceMemorySerialInterfaceDATA(D0)SerialModeDataAddressCLKCETCKTMSTDITDOOE/RESETCEODatads123_01_30603CFFIFigure2:XCFxxPPlatformFlashPROMBlockDiagramCLKOUTCEODATA(D0)(Serial/ParallelMode)D[1:7](ParallelMode)TCKTMSTDITDOCLKCEEN_EXT_SELOE/RESETBUSYDataDataAddressREV_SEL[1:0]CFControlandJTAGInterfaceMemoryOSCSerialor