电路仿真与实践实验报告第四次实验报告

电路仿真与实践实验报告第四次试验一、实验要求重点学习内容9.49.510.110.210.6习题：第九章1721第十章316二、实验环境WindowsXPMultisim11三、仿真内容与步骤1、实验1有源滤波电路（1）低通滤波器U1Rf10kΩRi10kΩC11nFV11Vpk1kHz0Deg570XBP1INOUT104一阶有源低通滤波器幅频响应相频响应U1Rf27kΩR116.8kΩC147nFUi1Vpk1kHz0DegR26.8kΩC247nFR347kΩ15002490二阶有源低通滤波器交流分析交流分析中读取的低通滤波器截止频率有误解决方案：调节坐标有得出截止频率约为507.2543HzU17413247651R17kΩC143nFC243nFR27kΩV31Vrms350Hz0°VCC5VVEE-15VXBP1INOUT二阶切比雪夫低通滤波器幅频特性相频特性（2）高通滤波器U1Rf20kΩR20kΩC1nFUi1Vpk1kHz0Deg560XBP1INOUT740一阶高通滤波器电路幅频特性U1Rf9.3kΩUi1Vpk1kHz0DegRa15.9kΩR115.9kΩC110nFR215.9kΩC210nFR310.6kΩR42kΩ60570010XBP1INOUT420二阶有源高通滤波器幅频特性R16.8kΩC14.7nFC24.7nFR213.5kΩR327kΩR447kΩV1500mVrms2kHz0°U13247651VCC15VVEE-15VXBP1INOUT巴特沃斯二阶高通滤波器幅频响应（3）带通滤波器U1Rf42.42kΩC115nFC215nFR21.21kΩRr3.03kΩV11Vpk1000Hz0Deg021XBP1INOUT530窄带带通滤波器幅频响应V115VV215VU17413247651R115kΩC151nFV315VV415VU27413247651R27.5kΩC251nFC35nFR37.5kΩC410nFR47.5kΩV51.414Vrms4kHz0°XBP1INOUT3阶带通滤波器仿真电路幅频响应（4）带阻滤波器U1R3400kΩC1220nFC2220nFR1200kΩR2800ΩV11Vpk60Hz0DegR410kΩR510kΩU2R610kΩXBP1INOUT025194008带阻滤波器的原理图幅频响应得出中心频率为40Hz（5）滤波器设计向导通带截止频率为3.4kHz，阻带起始频率为4kHz，通带最大衰减为-1dB，阻带最小衰减为-25dB的契比雪夫无源低通滤波器0Vvin750Ωrsource4.412mHL14.343mHL23.603mHL31.049mHL41.46µFC11.778µFC21.633µFC31.069µFC450Ωrload设计一个低端通带截止频率为1kHz，低端阻带起始频率为1.5kHz，高端阻带截止频率为2kHz，高端通带起始频率为3kHz，通带最大衰减为-1dB，阻带最小衰减为-25dB的巴特沃斯无源低通滤波器0Vvin750Ωrsource5.968mHLLL11.061µFCLC15.305mHLLL21.194µFCLC22.122µFCCC11.061µHLLC150Ωrload频率响应2、实验2信号产生电路（1）正弦波信号产生电路U17413247651R1100kΩKey=A35%R210kΩR310kΩR4100kΩC10.1µFC30.1µF00321XSC1ABExtTrig++__+_VCCVEEVEEVCC4基本文氏电桥振荡电路振荡电路振荡波形U1Rf2100kΩR120kΩR220kΩC2100nFC1100nFR510kΩKey=A50%Q1Rf138kΩC38µFD1R410kΩR310kΩ改进的文氏电桥振荡器U1R12kΩR22kΩR32kΩR4800kΩC11nFC21nFC31nF4251VoXSC1ABGT30RC移相式振荡器刚开始时振荡电路为一段时间后电路稳定U1R12kΩR24kΩKey=A50%C11µFC21µFC32µFR31000ΩR41000ΩR5500ΩD15VD25VR61000Ω104307680XSC1ABExtTrig++__+_20RC双T反馈式振荡器最初的振荡波形为在很短的时间后振荡波形变为（2）弛张振荡器U2R110kΩRf100kΩR2100kΩR4150kΩRo50kΩD24VC11nFU1Vo1Vo2XSC1ABGTD14V方波和三角波发生器电路一段时间后波形稳定3、实验3数字逻辑器件的测试（1）TTL门电路的测试U1A74LS00NVCC5VR1100ΩR21kΩKey=A15%U25.000V+-U31.136V+-TTL与非门电压传输特性测试图XSC1ABExtTrig++__+_VCC5VU1A74LS00NU1B74LS00NU1C74LS00N闭环振荡器U1A74LS125NVCC5VJ1Key=AJ2Key=BU1B74LS125NJ3Key=CJ4Key=DX1J2=1，U1A为高阻态U1A74LS125NVCC5VJ1Key=AJ2Key=BU1B74LS125NJ3Key=CJ4Key=DX1U1A74LS125NVCC5VJ1Key=AJ2Key=BU1B74LS125NJ3Key=CJ4Key=DX1J4=0，U1B输出为J3的逻辑状态（2）组合逻辑部件的功能测试U1A74LS183NA11CN14B13S161CN15VCC5VJ1Key=AJ2Key=BJ3Key=CX1X2全加器输出端SUM的测试U174LS151N~W6D04D13D22D31D415D514D613D712A11C9B10Y5~G7XLA1CQT1FVCC5VJ1Key=AJ2Key=BJ3Key=CV11kHz5VV22kHz5VV34kHz5VV46kHz5VV58kHz5VV610kHz5VV712kHz5VV824kHz5V多路选择器的功能测试电路工作波形（3）时序逻辑部件的功能测试U1A74LS74N1D21Q5~1Q6~1CLR11CLK3~1PR4V11kHz5VXLA1CQT1FV210Hz5VD触发器的功能测试电路U174LS160NQA14QB13QC12QD11RCO15A3B4C5D6ENP7ENT10~LOAD9~CLR1CLK2U2DCD_HEXXLA1CQT1FVCC5VV1100Hz5V74LS160逻辑功能的测试电路U174LS160NQA14QB13QC12QD11RCO15A3B4C5D6ENP7ENT10~LOAD9~CLR1CLK2U2DCD_HEXXLA1CQT1FVCC5VV1100Hz5VU174LS194NA3B4C5D6SL7QA15QB14QC13QD12SR2~CLR1S09S110CLK11X1X2X3X4VCCJ1Key=1J2Key=2J3Key=3J4Key=4J5Key=5J6Key=6J7Key=7J8Key=8J9Key=9V1100Hz5VVCC74LS194移位寄存器的功能测试电路启动仿真X4X3X2X1依次变亮（4）A/D与D/A功能测试U1ADC16VinVref+Vref-D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15SOCEOCV115VR12kΩKey=A55%VCC15VXLA1CQT1FV21kHz5VX1U2R2X2X3X4X5X6X7X8X9X10X11X12X13X14X15X16X17Probe1V:5.63VV(dc):5.63VAD转换器的功能测试电路启动仿真U1ADC16VinVref+Vref-D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15SOCEOCV115VR12kΩKey=A55%VCC15VXLA1CQT1FV21kHz5VX1U2R2X2X3X4X5X6X7X8X9X10X11X12X13X14X15X16X17Probe1V:5.63VV(dc):5.63VADC输出波形有误为在进行A/D与D/A功能测试时，启动仿真，ADC输出波形有误，从第一个上升沿后，6、5、9、17、18均为高电平，其余输出均为低电平。解决方案：实验中没有按照要求输入二进制数0110000000101001，输入此二进制数即得到正确结果。U1VDAC8D0D1D2D3D4D5D6D7OutputVref+Vref-V112VU20.234V+-VCC5VJ1Key=AJ2Key=BJ3Key=CJ4Key=DVCC5VJ5Key=EJ6Key=FJ7Key=CJ8Key=DU3U4VDAC型DA转换器的仿真电路U1VDAC8D0D1D2D3D4D5D6D7OutputVref+Vref-V112VU20.094V+-VCC5VJ1Key=AJ2Key=BJ3Key=CJ4Key=DVCC5VJ5Key=EJ6Key=FJ7Key=CJ8Key=DU3U44、实验4组合逻辑电路的仿真（1）用逻辑门实现2ASK、2FSK和2PSK电路的仿真U1A74S08NV11kHz5VV250Hz5VXSC1ABExtTrig++__+_2ASK键控调制电路输出波形下方为输出的2ASK键控调制波形。U1A74S04NU1B74S04NU2A74S08NU2B74S08NU3A74S02NV11kHz5VV21kHz5VV31kHz5VXSC1ABExtTrig++__+_2FSK键控调制电路B通道为2FSK键控调制电路输出波形。U2A7408NU2B7408NV1600Hz5VV2100Hz5VU1A7404NU1B7404NU3A7432NXSC1ABExtTrig++__+_2PSK键控调制电路（2）用四位全加器实现四位二进制的运算四位二进制数相加相减电路U274LS283NSUM_410SUM_313SUM_14SUM_21C49B411A412B315A314B22A23B16A15C07SC1AIO1IO1IO2IO2IO3IO3IO4IO4IO5IO5IO6IO6IO7IO7IO8IO8IO9IO9SC2BIO1IO1IO2IO2IO3IO3IO4IO4X1X2X3X4X5VCCJ1Key=MU274LS283NSUM_410SUM_313SUM_14SUM_21C49B411A412B315A314B22A23B16A15C07SC1AIO1IO1IO2IO2IO3IO3IO4IO4IO5IO5IO6IO6IO7IO7IO8IO8IO9IO9SC2BIO1IO1IO2IO2IO3IO3IO4IO4X1X2X3X4X5VCCJ1Key=MJ1=0时实现四位二进制数相加，当J1=1时实现四位二进制数相减。（3）编码器的扩展U174148NA09A17A26GS1431341522121110107463EI5EO15U274148NA09A17A26GS1431341522121110107463EI5EO15U3AU3BU3CVCC5VJ1J2J3J4J5J6J7J8J9J10J11J12J13J14J15J16GNDX1X2X3X4GND图中为8线-3线优先编码器扩展成16线-4线的优先编码器的输出是低电平有效，有开关J1~J16提供输入信号，编码器输出状态由探灯X1、X2、X3和X4表示。（4）用译码器实现逻辑函数U174LS138NY015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16~G2A4~G2B5J1Key=1J2Key=2J3Key=3VCC5VGNDGNDU2A74LS20NU2B74LS20NX1X2FCo由译码器实现全加器电路U174LS138NY015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16~G2A4~G2B5VCC5VGNDV15VV3100Hz5VABCDataR11X8SIP330Ω234516789VCCU174LS1