基于MIPS指令集的32位RISC处理器逻辑设计

本科生毕业论文题目：基于MIPS指令集的32位RISC处理器逻辑设计院系：信息科学与技术学院专业：计算机科学与技术学生姓名：李玮超学号：05373024指导教师：李国桢副教授二〇〇九年四月-i-摘要CPU是计算机系统的核心部件，在各类信息终端中得到了广泛的应用。处理器的设计及制造技术也是计算机技术的核心之一。MIPS是世界上很流行的一种RISC处理器。MIPS的意思是“无内部互锁流水级的微处理器”（Microprocessorwithoutinterlockedpipedstages），其机制是尽量利用软件办法避免流水线中的数据相关问题。本文在详细研究32位MIPS处理器体系结构的基础之上，在QuartusII7.2环境中，完全依靠自己的研发设计能力，采用硬件描述语言VHDL完成了拥有自主知识产权的基于MIPS指令集的32位RISC处理器的逻辑设计。共开发出单周期、多周期、五级流水线等3个不同版本的32位RISC处理器，均通过QuartusII进行了时序仿真和性能比较分析。本文的首先概述了MIPS指令集的重要特征，为讨论CPU的具体设计奠定基础。本文设计的3个版本的CPU均实现了一个共包含59条指令的32位MIPS指令子集。本文的主体部分首先详细描述了处理器各个独立功能模块的设计，为后续的整体设计实现提供逻辑功能支持。随后按照单周期、多周期、流水线的顺序，循序渐进的围绕着指令执行过程中需经历的五个阶段，详细描述了3个版本的处理器中各阶段的逻辑设计。在完成了各个版本的CPU的整体逻辑设计后，通过QuartusII时序仿真软件在所设计的CPU上运行了测试程序，测试输出波形表明了处理器逻辑设计的正确性。本文还通过QuartusII7.2中的QuartusIITimeQuestTimingAnalyzer软件，基于Altra公司的FPGA器件比较分析了所设计的3个版本CPU的性能。其中单周期CPU基于Altra公司的CycloneIII系列EP3C120F484C7器件综合的频率可达10.417MHz，而多周期CPU的综合频率可达12.935MHz，五级流水线CPU的综合频率可达12.376MHz。关键词：MIPS，处理器，单周期，多周期，流水线，VHDL-ii-AbstractCPUisacorecomponentofcomputersystem,whichhasbeenwidelyusedinavarietyofinformationdevicesindifferentareasofindustry.Processordesignandmanufacturingtechnologyisalsooneofthemostimportantcomputertechnologiesnowadays.MIPSisoneoftheworld-widepopularRISCprocessor.MIPSmeans“microprocessorwithoutinterlockedpipedstages”.Itsmechanismistomakefulluseofsoftwaretosolvethedata-relatedprobleminthepipeline.BasedonadetailedstudyofMIPSinstructionsetarchitecture,thispaperdescribesthelogicdesignofaMIPS-based32-bitRISCprocessorindetail,whichisdevelopedwithhardwaredescriptionlanguageVHDLinQuartusII7.2.Thedesignincludesthefollowingthreeversionsof32-bitRISCprocessor,thesingle-cycleversion,themulti-cycleversionandthe5-pipelineversion.AllthethreeversionshavebeentestedintheQuartusIItimingsimulationsoftwareenvironment.Aperformanceanalysisofthethreeversionsisgivenbythepaperaccordingtothetimingsimulationtestresults.Firstofall,thepaperprovidesanoverviewoftheimportantfeaturesoftheMIPSinstructionset,includingtheinstructionformat,instructionclassificationandtheaddressingmode,whichlaysthefoundationofthefollowingdiscussionaboutthespecificlogicdesign.A59-instructionsubsetof32-bitMIPSinstructionsethasbeenimplementedonallofthethreeprocessorversionsdiscussedinthepaper.Themainbodyofthepaperfirstdescribesindetailthelogicdesignoftheindependentfunctionalmodulesintheprocessors,providingfunctionalsupportforthefollow-upoveralldesign.Next,thearticledescribesthemostimportantlogicdesignsofthefiveinstructionexecutionstagesofthethreeprocessorversions,inaccordancewiththestep-by-stepsequenceofthesingle-cycleversion,themulti-cycleversionandthe5-pipelineversion.Uponthecompletionoftheoveralllogicdesignofeachprocessorversion,thecorrectnessofthelogicdesignisprovedbythewaveformoutputoftimingsimulationinQuartusIITimingSimulationSoftware.-iii-ThepaperalsogivesacomparativeperformanceanalysisofthethreeprocessorversionsaccordingtotheanalysisdataofQuartusIITimeQuestTimingAnalyzer.BasedontheAltraCycloneIIIseriesEP3C120F4847FPGAdevice,theinstructionexecutionfrequencyofthesingle-cycleprocessoris10.417MHz,whilethemulti-cycleprocessor’sis12.935MHzandthe5-pipelineprocessor’sis12.376MHz.Keywords:MIPS,CPU,single-cycle,multi-cycle,pipeline,VHDL-iv-目录第一章绪论..............................................................................................................................................11.1处理器概述................................................................................................................11.2处理器的设计过程与目标........................................................................................21.2.1处理器的设计过程.........................................................................................21.2.2处理器的设计目标.........................................................................................21.3本文的主要成果........................................................................................................31.4本文章节说明............................................................................................................4第二章MIPS体系结构概述.....................................................................................................................52.1复杂指令集与精简指令集的比较............................................................................52.2MIPS处理器简介.......................................................................................................62.3MIPS体系结构概述...................................................................................................72.3.1MIPS指令集简介............................................................................................72.3.2基于MIPS指令集进行设计的原因.............................................................122.4本设计实现的指令集系统......................................................................................12第三章处理器独立功能模块的设计....................................................................................................163.1辅助逻辑模块的设计..............................................................................................163.1.1译码器............................................