奇数偶数分频器

1奇数和偶数modulefdivsion_even_odd(clk,rst,count1,count2,clk_even,count,clk_odd);inputclk;inputrst;//声明输入信号clk,和rst；output[3:0]count;output[3:0]count1;output[3:0]count2;outputclk_even;outputclk_odd;//声明输入信号count,count1,count2,clk_even和clk_odd；even_divisioneven_division_1(.clk(clk),.rst(rst),.count1(count1),.count2(count2),.clk_even(clk_even));//对even_division程序例化；odd_divisionodd_division_1(.clk(clk),.rst(rst),.count(count),.clk_odd(clk_odd));endmodule//对odd_division程序例化；2odd_divisionmoduleodd_division(clk,rst,count,clk_odd);inputclk,rst;outputclk_odd;output[3:0]count;regclk_odd;reg[3:0]count;parameterN=8;always@(posedgeclk)if(!rst)begincount=1'b0;clk_odd=1'b0;endelseif(countN/2-1)begincount=count+1'b1;endelsebegincount=1'b0;clk_odd=~clk_odd;endendmoduleeven_divisionmoduleeven_division(clk,rst,count1,count2,clk_even);inputclk,rst;output[3:0]count1,count2;outputclk_even;reg[3:0]count1,count2;regclkA,clkB;wireclk_even;parameterN=9;assignclk_re=~clk;assignclk_even=clkA|clkB;always@(posedgeclk)if(!rst)begin3count1=1'b0;clkA=1'b0;endelseif(count1(N-1))begincount1=count1+1'b1;if(count1==(N-1)/2)beginclkA=~clkA;endendelsebeginclkA=~clkA;count1=1'b0;endalways@(posedgeclk_re)if(!rst)begincount2=1'b0;clkB=1'b0;endelseif(count2(N-1))begincount2=count2+1'b1;if(count2==(N-1)/2)beginclkB=~clkB;endendelsebeginclkB=~clkB;count2=1'b0;endendmodule