基于VHDL的SPWM程序

Ck模块为降频（1:3）fenpin模块：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityfenpintISport(clk:instd_logic;addout:outstd_logic_vector(9downto0));endfenpint;architectureoneoffenpintissignaladdr:std_logic_vector(9downto0);beginprocess(clk)beginifclk'eventandclk='1'thenaddr=addr+8;endif;endprocess;process(clk)beginifclk'eventandclk='1'thenaddout=addr;endif;endprocess;endone;Fenpint模块：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityfenpintISport(clk:instd_logic;addout:outstd_logic_vector(9downto0));endfenpint;architectureoneoffenpintissignaladdr:std_logic_vector(9downto0);beginprocess(clk)beginifclk'eventandclk='1'thenaddr=addr+8;endif;endprocess;process(clk)beginifclk'eventandclk='1'thenaddout=addr;endif;endprocess;endone;Compte模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcompteISPORT(clk:instd_logic;A:INSTD_LOGIC_VECTOR(7DOWNTO0);B:INSTD_LOGIC_VECTOR(7DOWNTO0);Y:OUTSTD_LOGIC);ENDcompte;ARCHITECTUREbehaveOFcompteISBEGINPROCESS(A,B,clk)BEGINifclk'eventandclk='1'thenIF(A=B)THENY='1';ELSEY='0';ENDIF;endif;ENDPROCESS;ENDbehave;三角载波和正弦波的值可用波形文件产生然后用分别添加到rom中正弦波某个点的值和三角波128个点的值比较，当正弦波的点值大于三角波的点值，则spwm输出1，否则输出零。Spwm输出接一个RC滤波器就可以输出比较漂亮的正弦波了（降低频率可提高幅度，当然最高只能3.3V，因为FPGA引脚输出的高电平为3.3V）