EDA与VHDL程序集锦

四选一选择器：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYWEIISPORT(a,b,c,d:STD_LOGIC;S0,S1:STD_LOGIC;Y:STD_LOGIC);ENDENTITY;ARCHITECTUREBHVOFWEIISSIGNALS:STD_LOGIC_VECTOR(1DOWNTO0);BEGINS=S0&S1;PROCESS(S)BEGINCASESISWHEN”00”=Y=’a’;WEAN”01”=Y=’b’;WHEN”10”=Y=’c’;WEAN”11”=Y=’d;WHENOTHERS=NULL;ENDCASE;ENDPROCESS;ENDBHV;条件语句：Y=aWHENS=”00”ELSEbWHENS=”11”ELSENULL;END;ENDPROCESS选择语句WITHSSELECTY=AWHEN“00”，’Z’WHENOTHERS;8_3编码器IF语句PORT(din:IN_STD_LOGIC_VECTOR(0-7)Output:OUT_STD_LOGIC_VECTOR(0_2);)ENDCRARCHITECTUREBEHAVOFCRISBEGINPROCESS(din)BEGINIF(din(7)=’0’)THENoutput=”000”;ELSEIF(din（6）=’0’)THENELSEoutput=”111”;ENDIFWHENELSE语句Output=”000”WHENdin（7）=‘0’ELSE;CASE语句CASE(din)ISWHENdin（7）=’0’=output=”000”;3_8译码器ENTITYDCISPORT(INPUT:INSTD_LOGIC_VECTOR(2_0)OUTPUT:OUTSTD_LOGIC__VECTOR(7-0);)PROCESS(INPUT)NEGINOUTPUT(0)=’1’WHENINPUT=”000”ELSE’0’;8位移位寄存器PORT(CLK,LOAD:INSTD_LOGIC;QB:OUTSTD_LOGIC;DIN:INSTD_LOGIC_VECTOR(7-0);DOUT:OUT_LOGIC_VECTOR(7-0);)ENDSHEF;ARCHITECTUREBEHAVOFSHFFISSIGNALREG8:STD_LOGIC_VECTOR(7-0);BEGINPROCESS(CLK,LOAD)BEGINIFCLK’EVENTANDCLK=’1’THEN;IFLOAD=’1’THENREG8=DIN;ELSEREG8(6-0)=REG8(7-1);ENDIF；ENDIF；ENDPROCESSQB=REG8(0);DOUT=REG8;ENDBEHAV;12进制计数器ENTITYCNT10ISPORT(CLK,RST,EN,LOAD:INSTD_LOGIC;DATA:INSTD_LOGIC_VECTOR(3-0);DOUT:OUTSTD_LOGIC_VECTOR(3-0)C1：OUT;E:IN;SI:OUT;y:buffer;step:in;model:inCOUT:OUTSTD_LOGIC);ENDCNT10;ARCHITECTUREBEHAVOFCNT10ISBEGINPROCESS(CLK,RST,EN,LOAD)VARIABLEQ:STD-LOGIC_VECTOR(3-0)BEGINIFRST=’0’THENQ:=(OTHER=’0’);ELSIFCLK’EVENTANDCLK=’1’THENIFEN=’1’THENIF(LOAD=’0’)THENQ:=DATA;ELSEIFQ11THENQ:=Q+1;ELSEQ:=(OTHER=’0‘)；ENDIF;ENDIF;ENDIF;ENDIF;IFQ=”1011”THENCOUT=’1’;ELSECOUT=’0’;ENDIF;DOUT=Q;ENDPROCESS;ENDBEHAV;可逆计数器：ADDSUB:INSTD_LOGICIFADDSUB=’1’THENQ=Q+1;ELSEQ=Q-1;模可变：PROCESS(CLK,E,STEP,MODEL)IF(CLK’EVENTANDCLK=’1’)THENIF(E=’1)THENIF(Y=UNSIGNED(MODEL))Y=”0000C1=1;ELSEY=Y+UNSIGNED(STEP);ENDIFELSEIF(Y=”0000”)THENY=UNSIGNED(MODEL)ZI=1ELSEY=Y-UNSIGNED(STEP);ENDIF8D锁存器PORT(CLR,CLK,ENA,OE:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7-0);Q:BUFFERSTD_LOGIC_VECTOR(7-0);)ENDARCHITECTUREBHVOFL8ISSIGNALQ1:STD_LOGIC_VECTOR(7-0);BEGINU1：PROCESS(CLK,CLR,ENA)BEGINIFCLR=’0’THENQ1=”00000000”ELSEIFCLK’EVENTANDCLK=’1’THENIFCENT=’1’THENQ1=D;ENDIFENDIFIFOE=’1’THENQ=Q1;ELSEQ=”ZZZZZZZZ”;ENDIF;ENDPROCESSU1ENDBHV三态门：PORT(ENABLE:INSTD_LOGICDATAIN:INSTD_LOGIC_VECTOR(7-0)DATAOUT:OUTSTD_LOGIC_VECTOR(7-0)BEGINPROCESS(ENABLE,ADTAIN)BEGINIFENABLE=’1THENDATAOUT=DATAIN;ELSEDATAOUT=”ZZZZZZZZ”;ENDIF;ENDPROCESSENDBHV求补码PORT(DIN:INSTD_OGIC_VECTOR(7-0)DOUT:OUTSTD_LOGIC_VECTOR(7-0)PROCESS(DIN)IF(DIN(7)=0)THENDOUT=DIN;ELSEDOUT=NOTDIN+1;DOUT(7)=NOTDOUT;ENDIFENDPROCESS分频器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALLUSEIEEE.STD_LOGIC_ARITH.ALLUSEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYEHATISPORT(CLKIN:INSTD_LOGIC;RESET:INSTD_LOGIC;CLKOUT:OUTSTDLOGIC)；ENDWHATARCHITECTUREBEHAVIORALOFWHATISSIGNALREG_CLK:STD_LOGIC:='0';BEGINCLKOUT=REG_CLK;PROCESS(CLKIN,RESET)VARIABLECNT:INTEGERRANGE0TO5:=0;BEGINIFRESET=0THENCNT:=0;REG_CLK='0';ELSIFRISING_EDGE(CLKIN)THENCNT:=CNT+1;IFCNT=5THENCNT:=0;REG_CLK=NOTREG_CLK;ENDIF;ENDIF;ENDPROGRESS;ENDBEHAVIORAL3-8译码器LIBRARYIEEEUSEIEEE.STD_LOGIC_1167.ALLUSEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYDC3TO8ISPort(DIN:INSTD_LOGIC_VECTOR(2-0);DOUT:OUTBIT_VECTOR（7-0））；ENDDC3TO8ARCHITECTUREBEHAVEOFDC3TO8ISBEGINDOUT=”00000001”SLLCONV_INTEGER(DIN)ENDBEHAVEBCD加法器PORT(DIN:INSTD_LOGIC_VECTOR(3-0)DIN2：INSTD_LOGIC_VECTOR(3-0)DIN3：OUTSTD_LOGIC_VECTOR(7-0)SIGINALADDS:STD_LOGIC_VECTOR(4-0)BEGINADDS=’0’&din1+’0’&din2Process(adds)IF(ADDS=”1001’)thenDOUT=ADDSELSEDOUT=ADDS+6;ENDIFENDPROCESSLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYs_machineISPORT(clk,reset:INSTD_LOGIC;state_inputs:INSTD_LOGIC_VECTOR(0TO1);comb_outputs:OUTINTEGERRANGE0TO15);ENDs_machine;ARCHITECTUREbehvOFs_machineISTYPEFSM_STIS(s0,s1,s2,s3);SIGNALcurrent_state,next_state:FSM_ST;BEGINREG:PROCESS(reset,clk)BEGINIFreset='1'THENcurrent_state=s0;ELSIFclk='1'ANDclk'EVENTTHENcurrent_state=next_state;ENDIF;ENDPROCESS;COM:PROCESS(current_state,state_Inputs)BEGINCASEcurrent_stateISWHENs0=comb_outputs=5;IFstate_inputs=00THENnext_state=s0;ELSEnext_state=s1;ENDIF;WHENs1=comb_outputs=8;IFstate_inputs=00THENnext_state=s1;ELSEnext_state=s2;ENDIF;WHENs2=comb_outputs=12;IFstate_inputs=11THENnext_state=s0;ELSEnext_state=s3;ENDIF;WHENs3=comb_outputs=14;IFstate_inputs=11THENnext_state=s3;ELSEnext_state=s0;ENDIF;ENDcase;ENDPROCESS;ENDbehv;8位锁存器PORT(CLK,RST:INSTD_LOGIC;DATA:INSTD_LOGIC_VECTOR(7DOWNTO0);MODE:INSTD_LOGICSHIFT_LEFT,SHIFT_RIGHT:INSTD_LOGIC;Q:BUFFERSTD_LOGIC_VECTOR(7DOWNTO0));ENDSHIFETER;AR…………………..BEGINPROCESS(CLKRST)BEGINWAITUNTIL(RISING_EDGE(CLK));IF(RST=’1’)THENQ=”0000000”;ELSECASE(MODE)ISWHEN“01”=Q=SHIFT_RIGHT&Q(7DOWNTO1);WHEN“10”=Q=Q(6DOWNTO0)&SHIFT_LEFT;左WHEN”11”=Q=DATA;WHENOTHERS=NULL;【VHDL常用的库：STDIEEEWORKVITAL】【TYPEST1ISARRAY(0TO15)OFSTD_LOGIC】【函数function（参数方式in）进程procedure（inoutinout）】【状态机设计有MOORE(输入输出无关)MEALY.MOORE(输入输出有关)】【EDA设计流程：设计输入（功能仿真）-综合-适配（时序仿真）-仿真-rtl描述】【PLD和CPLD(乘机项结构器件EEPROM【电可擦写编程器件】)FPGA(查找表结构器件SRAM)可编