VHDL程序设计-综合应用

第七章VHDL综合应用数字电子时钟显示电路ABEDCGF012345673-8译码器SEL2SEL1SEL0ABEDCGFB0B1B2B3B4B5B6B76个七段数码管SEGOUT(8)CLR时钟显示电路方框图CPFPGASELOUT(6)24进制计数器60进制计数器60进制计数器BCD七段译码电路BCD选择BCD(8)BIN(6)6个七段数码管扫描电路S(3)SEG(8)NUM(4)BCD(3-0)BCD(7-4)ENB(0)ENB(1)ENB(2)DBHDBMDBSBIN(6)时钟显示电路方框图SECCLRCYHCYSCYM分频器QCP38译码24进制计数器60进制计数器60进制计数器BCD七段译码电路BCD选择BCD(8)BIN(6)6个七段数码管扫描电路S(3)SEG(8)NUM(4)BCD(3-0)BCD(7-4)ENB(0)ENB(1)ENB(2)DBHDBMDBSBIN(6)时钟显示电路方框图SECCLRCYHCYSCYM分频器QCP38译码PROCESS(CP)BeginIFCP'EventANDCP='1'thenDLY=Q(21);Q=Q+1;ENDIF;ENDPROCESS;Free_Counter:BlockSignalQ:STD_LOGIC_VECTOR(24DOWNTO0);SignalDLY:STD_LOGIC;BeginPROCESS(CP)BeginIFCP'EventANDCP='1'thenDLY=Q(21);Q=Q+1;ENDIF;ENDPROCESS;SEC=Q(21)ANDNOTDLY;--about1HzS=Q(15DOWNTO13);--about250HzENB=001WHEN(S=0ORS=1)ELSE010WHEN(S=2ORS=3)ELSE100WHEN(S=4ORS=5)ELSE000;BIN=DBSWHENENB=001ELSEDBMWHENENB=010ELSEDBHWHENENB=100ELSE000000;EndBlockFree_Counter;--主文件声明代码COMPONENTCOUNTER60PORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY60:OUTSTD_LOGIC);ENDCOMPONENT;--子文件定义代码--***************************************************LIBRARYIEEE;USEIEEE.STD_LOGIC_UNSIGNED.ALL;--***************************************************ENTITYCOUNTER60ISPORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY60:OUTSTD_LOGIC);ENDCOUNTER60;--子文件定义代码ARCHITECTUREaOFCOUNTER60ISSIGNALQ:STD_LOGIC_VECTOR(5DOWNTO0);SIGNALRST,DLY:STD_LOGIC;BEGINPROCESS(CP,RST)BEGINIFRST='1'THENQ=000000;ELSIFCP'eventANDCP='1'THENDLY=Q(5);IFEC='1'THENQ=Q+1;ENDIF;ENDIF;ENDPROCESS;CY60=NOTQ(5)ANDDLY;RST='1'WHENQ=60ORCLR='1'ELSE'0';BIN=QWHENS='1'ELSE000000;ENDa;--主文件声明代码COMPONENTCOUNTER24PORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY60:OUTSTD_LOGIC);ENDCOMPONENT;--子文件定义代码--***************************************************LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;--***************************************************ENTITYCOUNTER24ISPORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY24:OUTSTD_LOGIC);ENDCOUNTER24;--子文件定义代码ARCHITECTUREaOFCOUNTER24ISSIGNALQ:STD_LOGIC_VECTOR(4DOWNTO0);SIGNALRST,DLY:STD_LOGIC;BEGINPROCESS(CP,RST)BEGINIFRST='1'THENQ=00000;ELSIFCP'eventANDCP='1'THENDLY=Q(4);IFEC='1'THENQ=Q+1;ENDIF;ENDIF;ENDPROCESS;CY24=NOTQ(4)ANDDLY;RST='1'WHENQ=24ORCLR='1'ELSE'0';BIN=('0'&Q)WHENS='1'ELSE000000;ENDa;Binary_BCD:BlockBEGINBCD=00000000WHENBIN=0ELSE00000001WHENBIN=1ELSE00000010WHENBIN=2ELSE00000011WHENBIN=3ELSE00000100WHENBIN=4ELSE00000101WHENBIN=5ELSE00000110WHENBIN=6ELSE00000111WHENBIN=7ELSE00001000WHENBIN=8ELSE00001001WHENBIN=9ELSE00010000WHENBIN=10ELSE00010001WHENBIN=11ELSE00010010WHENBIN=12ELSE00010011WHENBIN=13ELSE00010100WHENBIN=14ELSE00010101WHENBIN=15ELSE00010110WHENBIN=16ELSE00010111WHENBIN=17ELSE00011000WHENBIN=18ELSE00011001WHENBIN=19ELSE00100000WHENBIN=20ELSE00100001WHENBIN=21ELSE00100010WHENBIN=22ELSE00100011WHENBIN=23ELSE00100100WHENBIN=24ELSE00100101WHENBIN=25ELSE00100110WHENBIN=26ELSE00100111WHENBIN=27ELSE00101000WHENBIN=28ELSE00101001WHENBIN=29ELSE00110000WHENBIN=30ELSE00110001WHENBIN=31ELSE00110010WHENBIN=32ELSE00110011WHENBIN=33ELSE00110100WHENBIN=34ELSE00110101WHENBIN=35ELSE00110110WHENBIN=36ELSE00110111WHENBIN=37ELSE00111000WHENBIN=38ELSE00111001WHENBIN=39ELSE01000000WHENBIN=40ELSE01000001WHENBIN=41ELSE01000010WHENBIN=42ELSE01000011WHENBIN=43ELSE01000100WHENBIN=44ELSE01000101WHENBIN=45ELSE01000110WHENBIN=46ELSE01000111WHENBIN=47ELSE01001000WHENBIN=48ELSE01001001WHENBIN=49ELSE01010000WHENBIN=50ELSE01010001WHENBIN=51ELSE01010010WHENBIN=52ELSE01010011WHENBIN=53ELSE01010100WHENBIN=54ELSE01010101WHENBIN=55ELSE01010110WHENBIN=56ELSE01010111WHENBIN=57ELSE01011000WHENBIN=58ELSE01011001WHENBIN=59ELSE00000000;ENDBlockBinary_BCD;SELECT_BCD:BlockBEGINNUM=BCD(3DOWNTO0)WHEN(S=0ORS=2ORS=4)ELSEBCD(7DOWNTO4);EndBlockSELECT_BCD;SEVEN_SEGMENT:BlockBegin--gfedcbaSEG=0111111WHENNUM=0ELSE0000110WHENNUM=1ELSE1011011WHENNUM=2ELSE1001111WHENNUM=3ELSE1100110WHENNUM=4ELSE1101101WHENNUM=5ELSE1111101WHENNUM=6ELSE0000111WHENNUM=7ELSE1111111WHENNUM=8ELSE1101111WHENNUM=9ELSE1110111WHENNUM=10ELSE1111100WHENNUM=11ELSE0111001WHENNUM=12ELSE1011110WHENNUM=13ELSE1111001WHENNUM=14ELSE1110001WHENNUM=15ELSE0000000;EndBlockSEVEN_SEGMENT;延迟与微分电路用途：将宽脉冲减小为一个时钟周期的脉冲宽度；消除小于一个周期的脉冲CPINDCPQ#QDCPQ#QOUT延迟与微分电路时序图：CPINQ1Q2OUT同步计数器电路用途：消除竞争冒险；消除延时误差CPINDCPQ#QDCPQ#QECCLKQLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYTimer_DspisPORT(CP:INSTD_LOGIC;SEGOUT:OUTSTD_LOGIC_VECTOR(7DOWNTO0);SELOUT:OUTSTD_LOGIC_VECTOR(5DOWNTO0);CLEAR:INSTD_LOGIC);ENDTimer_Dsp;ARCHITECTUREaOFTimer_DspISCOMPONENTCOUNTER60PORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY60:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTCOUNTER24PORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY24:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALBIN:STD_LOGIC_VECTOR(5DOWN