基于FPGA的相位差测量模块的设计

基于FPGA的相位差测量模块的设计相位差测量设计思路相位差测量设计要求基于FPGA设计一个测量两路同频率信号相位差的模块，具体要求如下：测量信号频率范围：20Hz～20kHz，精度：2度，测量波形：方波。自行设计相位差可控双路输出脉冲源作为被测对象。发挥部分：（1）相位差和频率交替显示或同时显示（2）提高测量精度（3）拓宽频率范围到20Hz～200kHz（4）设计出一套相位计前置整形电路方案（采用模拟电路或者模数混合，仅设计和仿真，不制作），要求能自适应峰峰值在0.2V至5伏的非方波输入信号，尽量减少两路输入信号幅度不一致引入的误差，带宽不小于20Hz～20kHz，输出信号能接入本课题设计的相位差测量模块。相位差测量设计方案根据题目要求，我们组把这个模块的设计分为四个子模块，分别为：信号源的发生、频率计的设计、相位差的测量和四位LED相位差显示。信号源的发生产生两路同频、相位差可控的信号；频率计的设计是借用信号源产生的信号，然后根据内部晶振产生闸门宽度为1秒的闸门信号，在高电平时开始计数，记得的周期个数，即信号源产生信号的频率；相位差的测量是先通过测量两路信号的上升沿之间内部晶振的周期数，然后由此周期数换算出相位差，再通过VHDL语言内部函数转换成十进制数输出到显示模块。RTL图如下：模块程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYkzysISPORT(CLK:INSTD_LOGIC;KG:INSTD_LOGIC;ZS:INNATURAL;KG_OUT:OUTSTD_LOGIC);ENDentitykzys;ARCHITECTUREoneOFkzysISSIGNALCNT:NATURAL;BEGINPROCESS(KG,CLK)BEGINIFKG='0'THENCNT=0;KG_OUT='0';ELSIFCLK'EVENTANDCLK='1'THENIFCNTZSTHENCNT=CNT+1;ELSEKG_OUT='1';ENDIF;ENDIF;ENDPROCESS;END;libraryieee;useieee.std_logic_1164.all;entityxhkisport(sw_1:instd_logic_vector(4downto0);f_out1:outnatural;y_out2:outnatural);endxhk;architectureoneofxhkisbeginprocess(sw_1)begincasesw_1iswhen00001=f_out1=499999;y_out2=277778;when00010=f_out1=499999;y_out2=625000;when00011=f_out1=499999;y_out2=1666667;when00100=f_out1=6666;y_out2=5556;when00101=f_out1=6666;y_out2=11111;when00110=f_out1=6666;y_out2=16667;when00111=f_out1=499;y_out2=1806;when01000=f_out1=499;y_out2=1667;when01001=f_out1=499;y_out2=625;when01010=f_out1=82;y_out2=174;when01011=f_out1=82;y_out2=81;when01100=f_out1=82;y_out2=220;when01101=f_out1=49;y_out2=32;when01110=f_out1=49;y_out2=65;when01111=f_out1=49;y_out2=122;when10000=f_out1=0;y_out2=0;whenothers=f_out1=0;y_out2=0;endcase;endprocess;end;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYplfsqISPORT(clk:INSTD_LOGIC;ZS:INNATURAL;KG:INSTD_LOGIC;F_OUT:OUTSTD_LOGIC);END;ARCHITECTUREoneOFplfsqISSIGNALFULL:STD_LOGIC;BEGINPROCESS(clk)VARIABLECNT8:NATURAL;BEGINIFKG='0'THENFULL='0';CNT8:=ZS;ELSIFclk'EVENTANDclk='1'THENIFCNT80THENCNT8:=CNT8-1;ELSECNT8:=ZS;FULL=NOTFULL;ENDIF;ENDIF;ENDPROCESS;PROCESS(clk,FULL)BEGINIFKG='1'THENIFclk'EVENTANDclk='1'THENIFFULL='1'THENF_OUT='1';ELSEF_OUT='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;ENDone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYplfsqyISPORT(clk:INSTD_LOGIC;ZS:INNATURAL;KG:INSTD_LOGIC;F_OUTY:OUTSTD_LOGIC);END;ARCHITECTUREoneOFplfsqyISSIGNALFULL:STD_LOGIC;BEGINPROCESS(clk)VARIABLECNT8:NATURAL;BEGINIFKG='0'THENFULL='0';CNT8:=ZS;ELSIFclk'EVENTANDclk='1'THENIFCNT80THENCNT8:=CNT8-1;ELSECNT8:=ZS;FULL=NOTFULL;ENDIF;ENDIF;ENDPROCESS;PROCESS(clk,FULL)BEGINIFKG='1'THENIFclk'EVENTANDclk='1'THENIFFULL='1'THENF_OUTY='1';ELSEF_OUTY='0';ENDIF;ENDIF;ENDIF;ENDPROCESS;ENDone;信号源的发生：libraryieee;useieee.std_logic_1164.all;entityxhyisport(sw_1:instd_logic_vector(4downto0);clk:instd_logic;kg:instd_logic;f_outy:outstd_logic;f_out:outstd_logic);endxhy;architectureqqofxhyiscomponentxhkport(sw_1:instd_logic_vector(4downto0);f_out1:outnatural;y_out2:outnatural);endcomponent;componentkzysPORT(CLK:INSTD_LOGIC;KG:INSTD_LOGIC;ZS:INNATURAL;KG_OUT:OUTSTD_LOGIC);endcomponent;componentplfsqyPORT(clk:INSTD_LOGIC;ZS:INNATURAL;KG:INSTD_LOGIC;F_OUTY:OUTSTD_LOGIC);endcomponent;componentplfsqPORT(clk:INSTD_LOGIC;ZS:INNATURAL;KG:INSTD_LOGIC;F_OUT:OUTSTD_LOGIC);endcomponent;signala,b:NATURAL;signalc:STD_LOGIC;beginu1:xhkportmap(sw_1=sw_1,f_out1=a,y_out2=b);u2:kzysportmap(zs=b,clk=clk,kg=kg,kg_out=c);u3:plfsqyportmap(clk=clk,ZS=a,KG=C,F_OUTY=F_OUTY);u4:plfsqportmap(clk=clk,ZS=a,KG=KG,F_OUT=F_OUT);ENDARCHITECTUREqq;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt10isport(clk,en,clr:instd_logic;count10:bufferintegerrange0to400000000);endcnt10;architectureartofcnt10isbeginprocess(clk,clr,en)beginifclr='1'thencount10=0;elsifrising_edge(clk)thenif(en='1')thencount10=count10+1;endif;endif;endprocess;endart;频率计的设计：useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityfreq_measureisPort(clk0:instd_logic;wave1:instd_logic;q:outintegerrange0to400000000);endfreq_measure;architectureartoffreq_measureiscomponentcnt10port(clk,en,clr:instd_logic;count10:bufferintegerrange0to400000000);endcomponent;signalen1,clr1:std_logic;signaldate:integerrange0to400000000;beginprocess(clk0)variablecnt:integerrange0to6;beginifrising_edge(clk0)thenifcnt=0thenclr1='1';cnt:=1;elsifcnt5thencnt:=0;q=date;elsecnt:=cnt+1;clr1='0';en1='1';endif;endif;endprocess;u1:cnt10portmap(clk=wave1,en=en1,clr=clr1,count10=date);endart;libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitymeasure_nisPort(clk,clk0,clk1:instd_logic;n_out:outstd_logic_vector(15downto0));endmeasure_n;architectureartofmeasure_nissignalcount0,count01,count02,count1,count2:std_logic_vector(15downto0);signalx,y,a,clk10,clk11,clk20,clk21:std_logic;beginprocess(clk,clk0,clk1,x,y,count1,count2)beginifclk'eventandclk='1'thencaseaiswhen'0'=clk10=clk0;clk11=