第21届南京地区研究生通信年会论文集 D

779:PMPAMDAU1200AU1200WindowsCEAU1200WindowsCE:DesignofMediaPlayerBasedonAMDAU1200andWindowsCEEmbeddedSystemChenXinrong,PeiWenjiang(SoutheastUniversity;Departmentofradioengineering;NanjingChina;210096)Abstract:ThepaperanalysestheprojectofAMD’sembeddedprocessorbasedontheconceptandcharacteristicsofthePortableMediaPlayer(PMP).Followingthat,itgivesPMPhardwareandsoftwareprojectimplementationbasedonAU1200andWindowsCE,thenanalysestheAU1200’sinterfacedesignandthetransplantationofWindowsCE.Intheend,itsummarizestheprojectandprospectsthefatherwork.Keywords:PMP;embeddedprocessor;transplantationofembeddedsystemMP4PMPPMPAMDAlchemyAMDAU1200AU1200WindowsCEAU1200WindowsCEPMPSigmaDesignsEM851xAMDAlchemyPXA27xTIDM320DSPARMi.MX31SPCA536ZoranIttiamMediaAlbumPNX0190E[1]AMDAlchemy20051AMDAMDAlchemyAU1200AU1200PMPDVD[2]AU1200PMP[3]17801AU1200PMPAU1200PMPROMCODECLCDAU1200/MIPS32400mW@400MHzDDR1DDR2NANDFLASHMAEDSPUSB2.0HOSTDEVICELCDAES128/IISAC97SPISMBusWindowsCE5.0Linux2.6[1][2][2][3]22HYB18T512160AF-3.7512MDDR2SDRAM16bitAU1200FLASHS29GL128M10TAIR10128Mbit8bitSDSDWolfsonWM9712LEFL/VCODECIISAU1200LCD3.5in640480LCDLT1942CFSD/MMCUSB781333.3V2.5VVDDXOKPWRENPWREN1.2VAU1200AU1200WindowsCEWindowsCEWindowsCEWindowsCECPUBSPBSPPlatformBuilderBSPBootLoader,OALPlatformBuilder[4]BootLoaderBootLoaderRAMBootLoaderYAMONAutobootEBOOTWindowsCECP0FLASH44BOOTLOADERSFLASHYAMONCP0AutobootAutobootYAMON$tar–xvzfyamon-argon.tar.gz$cdyamon-argon$cdbin$vimakefile$makeinstall782YAMONJTAGBDIBDI_OXYGEN-TARGET:waitingfortargetVccBDI_OXYGEN-TARGET:waitingfortargetVccBDI_OXYGEN-TARGET:processinguserresetrequestBDI_OXYGEN-TargetIDcodeis0x1040228FBDI_OXYGEN-TargetIMPregis0x20404000BDI_OXYGEN-TARGET:resetingtargetpassedBDI_OXYGEN-TARGET:processingtargetstartup....BDI_OXYGEN-TARGET:processingtargetstartuppassedBDI_OXYGENeraseBDI_OXYGENprog0/yamon-02.27GDB1200.rec.mAutobootELFSRECBINFLASHSecureDigitalCardAutobootYAMONYAMONerase0xbfd00000d0000YAMONload/booter.rec.mYAMONgo0xbfd00000BSPKERNEL\HAL\ARM\fwxsc1.sEBOOT\main.cPMPFMAU1200PMPDSPDDR[1]GPSDVBTPMPPMPTV[1][1].AMDAlchemyAU1200.,2006,273-75.[2]AMDTechnologiesInc.AMDAlchemyAU1200DataSheet.[3]AMDTechnologiesInc.Aul200ProcessorApplicationGuide.[4].WindowsCE.NETXSCALE.,2004,17(4)30-31.783SRAM12Built-InSelf-TestDesignwithErrorCorrectionModuleforSRAMDengYudan1,WuNing2(CollegeofInformationScienceandTechnology,NanjingUniversityofAeronauticsandAstronautics,Nanjing,210016,China)Abstract:Inthispaper,wedescribetheBISTdesignforSRAMusingMARCHC-TBWtestalgorithmandtheerrorcheckingandcorrection(ECC)moduleisaddedinthisdesign.TheECCmoduleisbasedontheerrorcorrectionprincipleofHammingcodeandcodingalgorithm.AddingECCmoduleimprovesreliabilityofdataaccessinsystem.ThewholeBISTdesigniswritteninVerilogHDLandsimulatedinQuartusII.Theresultsshowthisdesign’sfeasibilityandimprovesystem’sstabilityandtestablilty.Keywords:BIST;MARCHC-TBW;ECCcode;datacorrectionBuilt-inSelf-testBIST2K×8bitSRAMMARCHCTBW[1]SRAMECC[2]SRAMSRAMSRAMVLSISRAM784[2][3]1AddressDecoderFault,AF2State-At-Faults,SAFTransitionFaults,TFCouplingFaults,CFNeighborhoodPatternSensitiveFaults,NPSFStateOpenFaults,SOF3DataRetentionFault,DRFMARCH[4]MARCH[5]MARCH[1]MARCHCTBWMARCHC-TBWMARCHC-TBMarchM0M15[1]MarchECCErrorCheckingandCorrection[2][6]ECC3bit(PP4,PP2,PP1)11ECC204828ECCecc_code226324bit1P8129,P8129’,P4096,P4096’,P2048,P2048’,1*,1*;P1024,P1024’,P512,P512’,P256,P256’,P128,P128’;P64,P64’,P32,P32’,P16,P16’,P8,P8’P4,P4’,P2,P2’,P1,P1’,1*,1*;“1*”1ecc_code1ecc_code2PP1=bit1⊕bit3⊕bit5⊕bit7PP1’=bit0⊕bit2⊕bit4⊕bit6PP2=bit2⊕bit3⊕bit6⊕bit7PP2’=bit0⊕bit1⊕bit4⊕bit5PP4=bit4⊕bit5⊕bit6⊕bit7PP4’=bit0⊕bit1⊕bit2⊕bit3785clksramwrreset—ready_outindata8bitecc_out32bitECCSRAMECCecc_code1BISTSRAMECCecc_code2ecc_code2BISTBISTecc_code1ecc_code2ecc_code3ecc_code31)02)14“1”P8P8’1001P8192,P4096,P2048,P1024,P512,P256,P128,P64,P32,P16,P8P4,P2,P13)1“1”ECC4)[7][8]SRAMSRAMBIST2BISTECCBISTControlbistmodeSRAMbistmode2ECCSRAMBISTBISTControladdr_generatedata_generateECCModuledata_compareSRAMunderTESTMUXsys_addrsys_datatest_addrtest_datadata_typecomp_resultecc_enaddr_entclkbistmodetest_resultsram_addrinputdataecc_code/F_codeweoecstest_donetest_startoutputdatacomp_data12048ECCCODE786bistmodeBIST2bistmodebistmodeControlecc_code1bistmodeControlecc_code2ecc_code1ecc_code2bistmodetest_starttest_donetest_resultF_codeQuartusIIverilogSRAMBIST2K×8bitSRAMEP20K200EFC484FPGABISTControl718ECC3181236(15%)32768memory(memory31%)bistmode0110204801H02H……07H08H……FFH00H……204801H02H……07H09H……FFH00H……(8)2048ecc_code133ECCbistmodetest_startecc_code/F_codetest_downtest_resulttclk7873bistmodeF_codeF_codeF_code1EF_code32048ecc_code2788[1]SRAM[J]2003.10Vol.8No.5[2]MichaelL.Bushnell,VishwaniD.Agrawal[M]2005.8.190-229[3]KarpovskyMG,YarmolikVNTransparentmemoryBIST[A]Proc.IEEEIntWorkshopMemoryTechnologyDesignandTesting1994106-111[4][]RochitRajsumanSoC[M]2003.8.118-137[5]vandeGoorADJ.Marchtestsforwordtoorientedmemories[A].DesignAutomationandTestinEurope1998Proceedings[C]1998501-508[6]S.[M]1976