ARM9教程DSP教程FPGA教程CPLD教程12A软硬件设计0229

第1页共23页ARM9教程DSP教程FPGA教程CPLD教程12A多核软硬件系统设计Actel_CoreMP7_UART第一部分原理图1.1Actel_CoreMP7_UART.SchDocCLK_BRDW17SWXW15JTAG_NEXUS_TMSJTAG_NEXUS_TCKJTAG_NEXUS_TDOJTAG_NEXUS_TDITCKTMSTDITDOTRSTJTAG.JTAGJTAGJTAGJTAGJTAG..U8INVSEL_I[3..0]WE_IDAT_O[31..0]DAT_I[31..0]ADR_I[12..0]ACK_OSTB_ICYC_IRST_ICLK_IBRAMControllerBRAM_DI[31..0]BRAM_DO[31..0]BRAM_A[10..0]BRAM_WEBRAM_ENBRAM_BW[3..0]U5WB_MEM_CTRLWishboneInterconnects0_STB_Os0_CYC_Os0_ACK_Is0_ADR_O[12..0]s0_DAT_I[31..0]s0_DAT_O[31..0]s0_SEL_O[3..0]s0_WE_Os0_CLK_Os0_RST_Om0_STB_Im0_CYC_Im0_ACK_Om0_ADR_I[31..0]m0_DAT_O[31..0]m0_DAT_I[31..0]m0_SEL_I[3..0]m0_WE_Im0_CLK_Im0_RST_IU4WB_INTERCONCLKDOUT[..]ADDR[..]DIN[..]WEENByteWE[..]M1RAMSEB/4U7CDIV4DC50INT_I[31..0]IO_CYC_OIO_CLK_OIO_ADR_O[23..0]IO_STB_OME_DAT_O[31..0]ME_SEL_O[3..0]ME_STB_OIO_WE_OIO_DAT_O[31..0]ME_WE_OIO_SEL_O[3..0]ME_ADR_O[31..0]ME_DAT_I[31..0]IO_ACK_IME_CYC_OME_ACK_IIO_DAT_I[31..0]IO_RST_OME_CLK_OME_RST_OMDU:InstalledDebugHardware:InstalledInternalMemory:2KBCoreMP7RISCProcessorCurrentConfigurationRST_ICLK_IU3COREMP7VCCWishboneInterconnects0_STB_Os0_CYC_Os0_ACK_Is0_ADR_Os0_DAT_I[7..0]s0_DAT_O[7..0]s0_SEL_O[3..0]s0_WE_Os0_CLK_Os0_RST_Os1_STB_Os1_CYC_Os1_ACK_Is1_ADR_O[3..0]s1_DAT_I[7..0]s1_DAT_O[7..0]s1_SEL_O[3..0]s1_WE_Os1_CLK_Os1_RST_Os1_INT_Im0_STB_Im0_CYC_Im0_ACK_Om0_ADR_I[23..0]m0_DAT_O[31..0]m0_DAT_I[31..0]m0_SEL_I[3..0]m0_WE_Im0_CLK_Im0_RST_Im0_INT_O[31..0]U2WB_INTERCONPortWishboneCYC_IACK_OSTB_IDAT_I[7..0]WE_ICLK_IRST_IADR_IDAT_O[7..0]PAO[7..0]PAI[7..0]PBO[7..0]PBI[7..0]U1WB_PRTIOLEDS[7..0]R4,P5,R2,T2,P2,N2,N6,N7SW[7..0]T4,U2,T5,U3,R6,P6,R5,P7CLK_IRST_IDAT_I[7..0]DAT_O[7..0]ADR_I[3..0]CYC_ISTB_IWE_IACK_OINT_OTXRXRXOU6SRL0_WTX0B11RX0G21U100CLKINTExampleprojectforActelCoreMP7DevKitBoardfittedwithM7A3PE600-FG484deviceResetThisexamplewillrunfromadirectorythatdoesnotcontainsspacecharacters.WithintheWindowsExplorer,gototheExamples\FPGAThirdPartyBoardsdirectoryandcopytheActel_CoreMP7_UARTfoldertotherootdirectoryofyourharddrivec:\orintoadirectorythatdoesnotcontainsspacecharacters.第2页共23页1.2hardware.h//..............................................................................//Automaticallygeneratedheaderfile.//Generated:3:57:03PM24/11/2008//Thisfileshouldnotbeedited.//..............................................................................#ifndef__HARDWARE_H__#define__HARDWARE_H__//..............................................................................#defineBase_GPIO0xFF000000#defineSize_GPIO0x00000002//..............................................................................//..............................................................................#defineBase_UART0xFF100000#defineSize_UART0x00000010#defineIntr_UART_A0//..............................................................................//..............................................................................#defineINTERRUPT_CONTROL_CFG0x00000001#defineINTERRUPT_KINDS_CFG0x00000000#defineINTERRUPT_EDGE_KIND_CFG0x00000000#defineINTERRUPT_LVL_KIND_CFG0x00000001//..............................................................................//..............................................................................#defineBase_irom0x00000000#defineSize_irom0x00000800第3页共23页//..............................................................................//..............................................................................#defineBase_xrom0x01000000#defineSize_xrom0x00001400//..............................................................................//..............................................................................#defineBase_xram0x01001400#defineSize_xram0x00000C00//..............................................................................//..............................................................................#define__COREMP7__#defineSRL0_W//..............................................................................#endif//__HARDWARE_H__第4页共23页1.3llpi_util_timing.h/*****************************************************************************\|*|*COPYRIGHT:Copyright(c)2004,PurPer|*|*DESCRIPTION:Timingutilityfunctions|*\*****************************************************************************/#ifndef__UTIL_TIMING_H__#define__UTIL_TIMING_H__voidtiming_set_clock_freq_hz(unsignedintfreq);unsignedinttiming_get_clock_freq_hz(void);unsignedlonglongtiming_get_tick_count(void);unsignedinttiming_get_tick_period_ns(void);unsignedinttiming_elapsed_time_ns(unsignedlonglongsince_tick);unsignedinttiming_elapsed_time_us(unsignedlonglongsince_tick);unsignedinttiming_elapsed_time_ms(unsignedlonglongsince_tick);unsignedlonglongtiming_get_ticks_ns(unsignedlonglongns);unsignedlonglongtiming_get_ticks_us(unsignedlonglongus);unsignedlonglongtiming_get_ticks_ms(unsignedlonglongms);voidtiming_delay_ns(unsignedlonglongns);voidtiming_delay_us(unsignedlonglongus);voidtiming_delay_ms(unsignedlonglongms);#endif第5页共23页1.4llpi_wb_srl0.h/***********************************************************************