CPLD FPGA使用方法及AHDL语言实验设计

第二章•CPLD/FPGA使用方法•AHDL语言•AHDL实验设计可编程逻辑器件的选择•CPLD,FPGAorASIC?–容量•宏单元数，逻辑单元数•寄存器数，门数•存储器大小–速度•Tpd–可用管脚数•固定输入管脚，可定义输入/输出管脚•工作电压–电源电压–接口电压•功耗•封装形式•配置方式–一次编程OTP(OneTimeProgrammable)–可再编程(Re-Programmable)•保持型，ISP•上电加载型，需要外置EPROMSelectionofCPLDorFPGA•Ifcircuithavingalotofcombinatoriallogic,useCPLD•IfcircuithavingalotofRegisterlogic,useFPGA100%combinatoriallogic0%Register0%combinatoriallogic100%RegisterCPLDFPGAcont...•SelectCPLDorFPGAdependson–thecircuitapplication•CPLDforCombinatorialLogicRegisterLogic•FPGAforRegisterLogicCombinatorialLogic–Gatecountneed•CPLDgatecountissmallerthanFPGA–SpeedGrade•CPLDhavinglesspintopinI/Odelay•CPLDingeneralrunfasterthanFPGA–Memoryneed•FPGAsupportMemory–Price•ingeneralFPGAislowerincostthanCPLDSelectGuideMAX7000SFamilyMembersFeatureUsablegatesMacrocellsMaxUserI/OtPD(ns)fcnt(MHz)7032/S60032365178.67064/S1,25064686151.570961,80096766151.57128/S2,5001281007.51257160/S3,2001601047.51257192/S3,750192124101007256/S5,00025616410100FLEX10KFamilyMembersFeature10K1010K2010K3010K4010K5010K10010K70Typicalgates10,00020,00030,00040,00050,000100,00070,000Logicelements5761,1521,7282,3042,8804,9923,744TotalRAMbits6,14412,28812,28816,38420,48024,57618,432TotalRegisters7201,3441,9682,5763,1845,3924,096MaxUserI/O150198248278310406358AvailableNowNowNowNowNowNowNowMulti-voltSystemGuideline•BothCPLDandFPGAfromAlterasupportMulti-voltsysteminterface•CouplesuggestionwhendoingMulit-voltdesign–5Vdevice,use70000S/10K/6K/8KA/9K–3.3Vdevice,use7000A/10KA/10KV/6KA/9KA–2.5Vdevice,use7000B/10KEcont...VCCINTGNDINTCoreVCCIOGNDIOVCCIOGNDIOUserOption:AllowsInterfaceto5.0-,3.3-&2.5-VSystemsVCCIOBasedonProcess:UserConnectstoPowerSupplyVCCINTcont...TypicalMinInputHighTypicalMaxInputLow5.0VTTL2.0V0.8VCMOS3.5V1.5V3.3VTTL2.0V0.8VCMOS2.0V0.8V2.5VCMOS1.6V0.7VInterfaceLogics5.0-VDeviceswithMultiVoltInterface(1)InputofDeviceDrivenbyAlteraDeviceOutputMustHave5.0-VTolerance.(2)InputofDeviceDrivenbyAlteraDeviceOutputMustHave3.3-VTolerance.(3)UseOpen-drainoutputswithpull-upto5.0V.ApplicableDevices:FLEX10K,FLEX6000,FLEX8000,MAX7000/S,MAX9000/A2.5V3.3V3.3V5.0V5.0V2.5V3.3V3.3V5.0V5.0VCMOSTTLCMOSTTLCMOSCMOSTTLCMOSTTLCMOS5.0V(1)(1)(1)3.3V(2)(3)InputLevelsOutputLevels5.0VVCCINTVCCIONote:Forsomeofthesmallerpackages,therearenoVCCIOpins,andthereforedoesnotsupportMulti-voltinterface.3.3-VDeviceswithMultiVoltInterfaceI(1)InputofDeviceDrivenbyAlteraDeviceOutputMustHave3.3-VTolerance.(2)UseOpen-drainoutputswithpull-upto5.0-V.ApplicableDevices:FLEX10KA,FLEX6000A,MAX7000A2.5V3.3V3.3V5.0V5.0V2.5V3.3V3.3V5.0V5.0VCMOSTTLCMOSTTLCMOSCMOSTTLCMOSTTLCMOS3.3V(1)(2)2.5VInputLevelsOutputLevels3.3VVCCINTVCCIOImportant:DonottietheVCCIOofthesedevicesto5.0-Vpowersource.Thiswilldamageourdevices.3.3-VDeviceswithMultiVoltInterfaceII(1)InputofDeviceDrivenbyAlteraDeviceOutputMustHave3.3-VTolerance.(2)UseOpen-drainoutputswithpull-upto5.0-V.ApplicableDevices:FLEX10KV,EPF8282AV,EPM7032V2.5V3.3V3.3V5.0V5.0V2.5V3.3V3.3V5.0V5.0VCMOSTTLCMOSTTLCMOSCMOSTTLCMOSTTLCMOS3.3V3.3V(1)(2)InputLevelsOutputLevelsVCCINTVCCIOImportant:DonottietheVCCIOofthesedevicesto5.0-Vor2.5-Vpowersource.Thiswilldamageourdevices.2.5-VDeviceswithMultiVoltInterface(1)InputofDeviceDrivenbyAlteraDeviceOutputMustHave3.3-VTolerance.(2)UseOpen-drainoutputswithpull-upto5.0-V.ApplicableDevices:FLEX10KE,FLEX10KB2.5V3.3V3.3V5.0V5.0V2.5V3.3V3.3V5.0V5.0VCMOSTTLCMOSTTLCMOSCMOSTTLCMOSTTLCMOS3.3V(1)(2)2.5VInputLevelsOutputLevels2.5VVCCINTVCCIOPackagingConsiderations•Engineering–PinCount–BoardSpaceEfficiency–PinCompatibilitywithOtherDevices–EasyPrototypeDevelopment•Manufacturing–BoardSpaceEfficiency–PCBTraceWidthRequirements–CompatibilitywithSolderReflowProcess–Quality/Yield/Cost841001602082403041001442563566001002564846721.40.61.51.51.92.90.40.81.11.93.10.20.40.81.160160100140120100250200200180190500600600600PackagingMetricsPLCCPQFP(RQFP)TQFPStandardBGA(1.27-mmPitch)FineLineBGA(1.0-mmPitch)1.270.650.650.500.500.500.500.501.271.271.271.001.001.001.0029x2914x2328x2828x2832x3240x4014x1420x2027x2735x3545x4511x1117x1723x2327x27PinCountBoardArea(in2)PinDensity(Pins/in2)Lead/BallPitch(mm)BodySize(mm)PackageTypeDecliningUsageMainstreamUsageAdvancedUsagePQFPTQFPTQFPPQFPStandardBGAStandardBGATQFPMicroBGATQFPFineLineBGAStandardBGAFineLineBGAFineLineBGAPDIPPLCCPQFPPGAPGA100Pins100to144145to240Above240DecliningMainstreamAdvancedPinCount/UsagePackagingTechnologyforPLDsHigherGateCountHasDrivenHigherPinCountDecliningUsageMainstreamUsageAdvancedUsage常用封装形式84-PinPlasticJ-LeadChipCarrier(PLCC)100-PinPlasticThinQuadFlatPack(TQFP)208-PinPlasticQuadFlatPack(PQFP)功耗•FPGA/CPLD不同芯核电压器件流行趋势资料来源：美国Altera公司0%20%40%60%80%100%19921993199419951996199719981999200020015.0V3.3V2.5V1.8V初始设计百分比PowerConsumptionImprovements0246810PowerConsumption(W)EPF10K50EPF10K1003.3-VFLEX10KA5.0-VFLEX10K3.3-VPowerSupplyReducesPowerConsumptionP=VIwhere:P=PowerV=VoltageI=CurrentISP/ICRIncreasesFlexibilityNoDeviceHandlingNoBentLeadsAllowsGenericInventoryEasyPrototypingSupportsChangesduringManufacturing/TestFlowAllow