EDA作业new

1名词解释：8小题，共16分EDA术语的英文全称和中文翻译基本上是作业中布置的EDA、ESDA、FPGA、PLD、CPLD、HDL、VHDL、CAD、CAE、CDE、PAL、GAL、SOC、SOPC、ASIC、CE、RTL、ISP、IP、ASSP、PCB、VDSM、IEEE、DFF、BCD、LPM、FSM、RAM、ROM、FIFO、EPROM、EEPROM、PIA、SRAM、OLMC、LUT、LE/LC、LAB、EAB、JTAG2填空题：共14分范围较广，都是基本概念简答题：2小题，共10分综合的概念及分类自顶向下设计信号与变量的区别状态机的分类状态机的基本组成进程组成，进程的顺序描述语句查找表原理3分析设计题：5小题，共60分1.数码管译码电路2.N进制的计数器3.移位寄存器(左移，右移，循环移位等）4.描述ROM，RAM5.已知输入与输出关系的组合电路描述6.元件例化语句7.N分频电路8.3－8译码器9.已知电路图用VHDL描述（D触发器,T触发器，电平触发型寄存器）10.已知状态转换图写状态机，或已知状态机画状态转换图（两进程或单进程）4作业1参考答案EDA:ElectronicDesignAutomation电子设计自动化ESDA：ElectronicSystemDesignAutomation电子系统设计自动化FPGA：FieldProgrammableGatesArray现场可编程门阵列PLD:ProgrammableLogicDevices可编程逻辑器件CPLD：ComplexProgrammableLogicDevice复杂可编程逻辑器件HDL:HardwareDescriptionLanguage硬件描述语言VHDL:VHSIC(VeryHighSpeedIntegratedCircuit)HardwareDescriptionLanguage超高速集成电路硬件描述语言CAD:ComputerAidedDesign计算机辅助设计CAE:ComputerAidedEngineering计算机辅助工程CDE:ConceptDriverEngineering概念驱动工程PAL_ProgrammableArrayLogic可编程逻辑阵列GAL_GenericArrayLogic通用阵列逻辑5SOC:SytemOnaChip片上系统SOPC:SystemOnaProgrammableChip片上可编程系统ASIC:ApplicationSpecificIntegratedCircuits专用集成电路CE：ConcurrentEngineering并行设计工程RTL:RegisterTransportLevel寄存器传输级ISP:InSystemProgram系统在线编程IP:IntellectualProperty知识产权ASSP:ApplicationSpecificStandardProduct专用标准产品PCB:PrintedCircuitBoard印刷电路板VDSM:VeryDeepSub-Micron超深亚微米IEEE:InstituteofElectricalandElectronicEngineers电气和电子工程师学会6作业五1.用VHDL设计一个占空比1:2的三分频电路。2.用VHDL设计一个占空比1:1的三分频电路。EPROM:ElectricallyProgrammableRead-Only-Memory电可编程只读存储器EEPROM:ElectricallyErasableProgrammableRead-OnlyMemoryPIA:ProgrammableInterconnectArray可编程连线阵SRAM:静态随机存储器OLMC:OutputLogicMacroCell输出逻辑宏单元LUT:LookUpTable查找表LE/LC:LogicElement/LogicCell逻辑单元LAB:LogicArrayBlock逻辑阵列块EAB:EmbeddedArrayBlock嵌入式阵列块JTAG:JointTestActionGroup联合测试行动组4.6p94•libraryieee;•useieee.std_logic_1164.all;•entitymx3256is•port(ina,inb,inck,inc:instd_logic;•E,OUT1:outstd_logic);•end;•architecturebehavofmx3256is•signala,b,s,Q:std_logic;•componentlk35is•port(A1,A2,clk:instd_logic;•Q1,Q2:outstd_logic);•endcomponent;•begin•8u1:lk35portmap(A1=ina,A2=inb,clk=inck,Q1=b,Q2=s);u2:lk35portmap(A1=s,A2=Q,clk=inck,Q1=a,Q2=out1);E=awhens='1'elseb;p1:process(inck)beginifinc='1'thenQ='0';elseifinck'eventandinck='1'then--rising_edge(inck)Q=S;endif;endif;endprocess;end;4.7p94•libraryieee;•useieee.std_logic_1164.all;•useieee.std_logic_unsigned.all;•entitycounter16is•port(clr,en,clk,ctrl:instd_logic;•Q:outstd_logic_vector(15downto0));•end;•architecturebehavofcounter16is•signalQ1:std_logic_vector(15downto0);•begin•process(clk,en,clr,ctrl)•begin•9•ifclr='1'thenQ1=(others='0');•elsifclk'eventandclk='1'then•ifen='1'then•ifctrl='1'then•Q1=Q1+1;•else•Q1=Q1-1;•endif;•endif;•endif;•endprocess;••Q=Q1;••end;115.8p1247人表决电路libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityvoteisport(A:instd_logic_vector(7downto1);green:outstd_logic;red:outstd_logic);end;architecturebhvofvoteisbeginprocess(a)variabletemp:std_logic_vector(2downto0);begintemp:=000;ifa(7)='1'thentemp:=temp+1;endif;ifa(6)='1'thentemp:=temp+1;endif;ifa(5)='1'thentemp:=temp+1;endif;ifa(4)='1'thentemp:=temp+1;endif;ifa(3)='1'thentemp:=temp+1;endif;ifa(2)='1'thentemp:=temp+1;endif;ifa(1)='1'thentemp:=temp+1;endif;iftemp3thengreen='1';red='0';elsegreen='0';red='1';endif;endprocess;end;127人表决电路libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityvoteisport(A:instd_logic_vector(7downto1);green:outstd_logic;red:outstd_logic);end;architecturebhvofvoteisbeginprocess(a)variabletemp:std_logic_vector(2downto0);begintemp:=000;foriin7downto1loopifa(i)='1'thentemp:=temp+1;endif;endloop;iftemp3thengreen='1';red='0';elsegreen='0';red='1';endif;endprocess;end;137人表决电路方法二libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;USEieee.std_logic_arith.all;entityvoteisport(A:instd_logic_vector(7downto1);green:outstd_logic;red:outstd_logic);end;architecturebhvofvoteisbeginprocess(a)variabletemp:integerrange0to7;begintemp:=0;FORiIN7downto1LOOPtemp:=temp+conv_integer(a(i));ENDLOOP;--temp:=CONV_INTEGER(a(1))+CONV_INTEGER(a(2))+CONV_INTEGER(a(3))+CONV_INTEGER(a(4))+CONV_INTEGER(a(5))+CONV_INTEGER(a(6))+CONV_INTEGER(a(7));iftemp3thengreen='1';red='0';elsegreen='0';red='1';endif;endprocess;end;147人表决电路方法三libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityvoteisport(A:instd_logic_vector(7downto1);green:outstd_logic;red:outstd_logic);end;architecturebhvofvoteisbeginprocess(a)variabletemp:std_logic_vector(2downto0);begintemp:=000;temp:=(00&a(7))+a(6)+a(5)+a(4)+a(3)+a(2)+a(1);iftemp3thengreen='1';red='0';elsegreen='0';red='1';endif;endprocess;end;155.10答案：方法一:用变量libraryieee;useieee.std_logic_1164.all;entitydcntvisport(clk:instd_logic;dout:outstd_logic_vector(2downto0));end;architecturebhvofdcntvisbeginprocess(clk)variabletemp:std_logic_vector(2downto0);beginifclk'eventandclk='1'thencasetempiswhen000=temp:=001;when001=temp:=011;when011=temp:=111;when111=temp:=101;when101=temp:=100;when100=temp:=000;whenothers=temp:=000;endcase;endif;d