深圳大学-数字集成电路(中文)第六章剖析

EE141©DigitalIntegratedCircuits2ndCombinationalCircuits1第六章CMOS组合逻辑门的设计Nov9,2011EE141©DigitalIntegratedCircuits2ndCombinationalCircuits2组合逻辑与时序逻辑组合逻辑时序逻辑Output=f(In)Output=f(In,PreviousIn)CombinationalLogicCircuitOutInCombinationalLogicCircuitOutInStateEE141©DigitalIntegratedCircuits2ndCombinationalCircuits3每一时刻(除了切换期间的瞬态效应）每个门的输出通过一个低阻路径连接到在任何时候该门的输出即为该电路实现的布尔函数值(再一次忽略切换期间的瞬态效应)不同于动态电路，后者依赖把信号值暂时存放在高阻抗电路节点的电容上静态CMOS电路设计VDDorVssEE141©DigitalIntegratedCircuits2ndCombinationalCircuits4静态互补CMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOSonlyNMOSonlyPUN(上拉网络)和PDN(下拉网络)是双通道逻辑网络EE141©DigitalIntegratedCircuits2ndCombinationalCircuits5构成PUN和PDN网络一个晶体管可以看成是一个由其栅信号控制的开关PDN由NMOS器件构成，PUN由PMOS器件构成可以推导出一组规则来实现逻辑功能互补CMOS结构的上拉和下拉网络互为对偶网络互补门本质上是反相的，只能实现与非、或非和异或门实现一个具有N个输入的逻辑门需晶体管数目2N个EE141©DigitalIntegratedCircuits2ndCombinationalCircuits6NMOS晶体管的串并联结TransistorscanbethoughtasaswitchcontrolledbyitsgatesignalNMOSswitchcloseswhenswitchcontrolinputishighNMOS逻辑规则---串联AND操作、并联OR操作EE141©DigitalIntegratedCircuits2ndCombinationalCircuits7PMOS晶体管的串并联结PMOS逻辑规则---串联NOR操作、并联NAND操作EE141©DigitalIntegratedCircuits2ndCombinationalCircuits8NMOS—下拉器件PMOS—上拉器件VDDVDD0PDN0VDDCLCLPUNVDD0VDD-VTnCLVDDVDDVDD|VTp|CLSDSDVGSSSDDVGSEE141©DigitalIntegratedCircuits2ndCombinationalCircuits9互补CMOS逻辑类型PUN和PDN是互补网络–符合DeMorgan定律–单级互补CMOS逻辑门是反相输出的–同相：需加额外反相EE141©DigitalIntegratedCircuits2ndCombinationalCircuits10ExampleGate:NANDEE141©DigitalIntegratedCircuits2ndCombinationalCircuits11ExampleGate:NOREE141©DigitalIntegratedCircuits2ndCombinationalCircuits12构成一个复合门C(a)pull-downnetworkSN1SN4SN2SN3DFFADBCDFABC(b)Derivingthepull-upnetworkhierarchicallybyidentifyingsub-netsDAABCVDDVDDB(c)completegateEE141©DigitalIntegratedCircuits2ndCombinationalCircuits13复合CMOS门OUT=D+A•(B+C)DABCDABCEE141©DigitalIntegratedCircuits2ndCombinationalCircuits14EE141单元设计标准单元通用逻辑可综合等高，宽度可变数据通路单元规则、结构化逻辑（算术运算）单元中包含互连线固定高度和宽度数字集成电路14组合逻辑电路EE141©DigitalIntegratedCircuits2ndCombinationalCircuits15标准单元不包含维数信息表示了晶体管间的相对位置EE141©DigitalIntegratedCircuits2ndCombinationalCircuits16标准单元EE141©DigitalIntegratedCircuits2ndCombinationalCircuits17棍棒图不包含维数信息表示了晶体管间的相对位置InOutVDDGNDInverterAOutVDDGNDBNAND2EE141©DigitalIntegratedCircuits2ndCombinationalCircuits18棍棒图CABX=C•(A+B)BACijABCEE141©DigitalIntegratedCircuits2ndCombinationalCircuits19C•(A+B)的两个版本XCABABCXVDDGNDVDDGNDEE141©DigitalIntegratedCircuits2ndCombinationalCircuits20棍棒图逻辑图CABX=C•(A+B)BACijjVDDXXiGNDABCPUNPDNABC逻辑图EE141©DigitalIntegratedCircuits2ndCombinationalCircuits21X逻辑图CABX=(A+B)•(C+D)BADVDDXXGNDABCPUNPDNCDDABCDEE141©DigitalIntegratedCircuits2ndCombinationalCircuits22例:x=ab+cdGNDxabcdVDDxGNDxabcdVDDx(a)Logicgraphsfor(ab+cd)(b)EulerPaths{abcd}acdxVDDGND(c)stickdiagramforordering{abcd}bEE141©DigitalIntegratedCircuits2ndCombinationalCircuits23互补CMOS组合逻辑特性静态特性高噪声容限(NM)VOH=VDD,VOL=VSS(GND)无静态功耗稳态时，VDD和VSS(GND)间无直流通路动态特性上升、下降时延接近上下网络有适当的尺寸比例EE141©DigitalIntegratedCircuits2ndCombinationalCircuits24CMOS特性满电源幅度开关;高噪声容限电平幅度与器件尺寸无关;ratioless稳态时总有到VDD或GND之间的通路;低输出阻抗高输入阻抗;输入稳态电流几乎为零电源与地之间无直接通路;无静态功耗传输延时是负载电容和晶体管电阻的函数EE141©DigitalIntegratedCircuits2ndCombinationalCircuits25开关延时模型AReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintNAND2INVNOR2EE141©DigitalIntegratedCircuits2ndCombinationalCircuits26输入波形对延时的影响延时与输入波形有关输出高到低的转换A=B=0-1–延时：0.69(2Rn)CLA=1，B=0-1-延时：0.69(2Rn)CLA=0-1，B=1–延时：0.69(2Rn)CL–实际上单A跳变比单B跳变快CLARnARpBRpBRnCintEE141©DigitalIntegratedCircuits2ndCombinationalCircuits27输入波形对延时的影响延时与输入波形有关输出低到高的转换A=B=1-0–延时：0.69Rp/2CLA=1，B=1-0-延时：0.69RpCLA=1-0，B=1–延时：0.69RpCL–实际上单A跳变比单B跳变快CLARnARpBRpBRnCintEE141©DigitalIntegratedCircuits2ndCombinationalCircuits28延时对输入波形的依赖-0.500.511.522.530100200300400A=B=10B=1,A=10B=10,A=1time[ps]Voltage[V]InputDataPatternDelay(psec)A=B=0169A=1,B=0162A=01,B=150A=B=1035A=1,B=1076A=10,B=157NMOS=0.5m/0.25mPMOS=0.75m/0.25mCL=100fFEE141©DigitalIntegratedCircuits2ndCombinationalCircuits29扇入的考虑DCBADCBACLC3C2C1分布RC模型(Elmore延时)tpHL=0.69Reqn(C1+2C2+3C3+4CL)传输延时随扇入迅速恶化-最坏情况成平方关系-电阻电容同时起作用EE141©DigitalIntegratedCircuits2ndCombinationalCircuits30tp：扇入的函数tpLHtp(psec)fan-in避免扇入大于4的门025050075010001250246810121416tpHL平方线性tptpLHEE141©DigitalIntegratedCircuits2ndCombinationalCircuits31tp扇出的函数246810121416tpNOR2tp(psec)eff.fan-out所有的门具有相同驱动电流tpNAND2tpINV斜率是驱动力的函数EE141©DigitalIntegratedCircuits2ndCombinationalCircuits32tp：扇入和扇出的函数扇入:平方源于电容和电阻的增加扇出:每个额外扇出增加负载CLEE141©DigitalIntegratedCircuits2ndCombinationalCircuits33复杂门快速设计1晶体管尺寸规则只要扇出电容为主渐进尺寸规则InNCLC3C2C1In1In2In3M1M2M3MN分布RC线M1M2M3…MN(最接近输出最小)使R1R2R3…RNEE141©DigitalIntegratedCircuits2ndCombinationalCircuits34复杂门快速设计2晶体管排序C2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcriticalpathcriticalpath放电101放电放电1延时由CL,C1andC2的放电时间决定延时由CL的放电时间决定1101放电放电结束放电结束EE141©DigitalIntegratedCircuits2ndCombinationalCircuits35复杂门快速设计3不同的逻辑结构F=ABCDEFGHEE141©DigitalIntegratedCircuits2ndCombinationalCircuits36复杂门快速设计4插入缓冲器将扇入和扇出隔离开CLCLEE141©DigitalIntegratedCircuits2ndCombinationalCircuits37EE141晶体管尺寸规则假定典型p/n管比例为2/1—并联保持(考虑单个跳变；同时跳变时电阻，并联速度更快)—串联加倍(考虑同时跳变时，电阻