寄存器和加减乘除程序

11、8位寄存器代码LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYREGISPORT(clk,RST:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYREG;ARCHITECTURErt1OFREGISBEGINPROCESS(D,clk,RST)BEGINIFRST='1'THENQ=00000000;ELSIF(clk='1'ANDclk'EVENT)THENQ=D;ENDIF;ENDPROCESS;ENDARCHITECTURErt1;仿真波形图如下，请把CLK周期改成自己的学号后仿真。22．寄存器组代码libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityREG4X8isPort(G,CLK:instd_logic;S:inINTEGERRANGE0TO3;X:instd_logic_vector(7downto0);Y:OUTstd_logic_vector(7downto0));endREG4X8;architectureBehavioralofREG4X8istypexINisarray(0to3)ofstd_logic_vector(7downto0);signalqxIN:xIN:=((others=00000000));beginprocess(Clk,G,S,QXIN)beginIFG='0'THENY=qxIN(S);ELSif(rising_edge(clk))thenqxIN(S)=X;endif;endprocess;endBehavioral;仿真波形图如下，请把CLK周期改成自己的学号后仿真。33.加减法电路程序(1)超前进位模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCQJWISPORT(G1,G2,G3,G4,P1,P2,P3,P4,cin:INSTD_LOGIC;C1,C2,C3,C4:OUTSTD_LOGIC);ENDENTITYCQJW;ARCHITECTURErt1OFCQJWISBEGINC1=(P1ANDCIN)ORG1;C2=(p2andp1andcin)or(P2ANDG1)ORG2;C3=(P3ANDp2andp1andcin)or(P3ANDP2ANDG1)OR(P3ANDG2)ORG3;C4=(P4ANDP3ANDp2andp1andcin)or(P4ANDP3ANDP2ANDG1)OR(P4ANDP3ANDG2)OR(P4ANDG3)ORG4;ENDARCHITECTURErt1;（2）GP模块LIBRARYIEEE;4USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYGPISPORT(A,B:INSTD_LOGIC;G,P:OUTSTD_LOGIC);ENDENTITYGP;ARCHITECTURErt1OFGPISBEGING=AANDB;P=AXORB;ENDARCHITECTURErt1;（3）一位加法器模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYADDISPORT(A,B,C:INSTD_LOGIC;F:OUTSTD_LOGIC);ENDENTITYADD;ARCHITECTURErt1OFADDISBEGINF=AXORBXORC;ENDARCHITECTURErt1;（4）四位加法器模块5LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYADD4ISPORT(A,B:INSTD_LOGIC_VECTOR(4DOWNTO1);CIN:INSTD_LOGIC;COUT:OUTSTD_LOGIC;F:OUTSTD_LOGIC_VECTOR(4DOWNTO1));ENDENTITYADD4;ARCHITECTURErt1OFADD4ISCOMPONENTADDPORT(A,B,C:INSTD_LOGIC;F:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTGPPORT(A,B:INSTD_LOGIC;G,P:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTCQJWPORT(G1,G2,G3,G4,P1,P2,P3,P4,CIN:INSTD_LOGIC;C1,C2,C3,C4:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALC1,C2,C3,C4:STD_LOGIC;SIGNALG1,G2,G3,G4:STD_LOGIC;SIGNALP1,P2,P3,P4:STD_LOGIC;BEGINU1:GPPORTmap(A(1),b(1),G1,P1);6U2:GPPORTmap(A(2),b(2),G2,P2);U3:GPPORTmap(A(3),b(3),G3,P3);U4:GPPORTmap(A(4),b(4),G4,P4);U5:CQJWPORTmap(G1,G2,G3,G4,P1,P2,P3,P4,CIN,C1,C2,C3,C4);U6:ADDPORTmap(A(1),b(1),CIN,f(1));U7:ADDPORTmap(A(2),b(2),c1,f(2));U8:ADDPORTmap(A(3),b(3),c2,f(3));U9:ADDPORTmap(A(4),b(4),c3,f(4));COUT=C4;ENDARCHITECTURErt1;（5）四异或模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYM4xorISPORT(A:INSTD_LOGIC_VECTOR(4DOWNTO1);M:INSTD_LOGIC;B:OUTSTD_LOGIC_VECTOR(4DOWNTO1));ENDENTITYM4xor;ARCHITECTURErt1OFM4xorISBEGINB(1)=A(1)XORM;B(2)=A(2)XORM;B(3)=A(3)XORM;B(4)=A(4)XORM;ENDARCHITECTURErt1;7（6）溢出判断模块LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYADDISPORT(A,B,C:INSTD_LOGIC;F:OUTSTD_LOGIC);ENDENTITYADD;ARCHITECTURErt1OFADDISBEGINF=AXORBXORC;ENDARCHITECTURErt1;（7）加减运算器主程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYaddsubISPORT(A,B:INSTD_LOGIC_VECTOR(4DOWNTO1);M:INSTD_LOGIC;yc:OUTSTD_LOGIC;y:OUTSTD_LOGIC_VECTOR(4DOWNTO1));ENDENTITYaddsub;ARCHITECTURErt1OFaddsubISCOMPONENTADD48PORT(A,B:INSTD_LOGIC_VECTOR(4DOWNTO1);CIN:INSTD_LOGIC;COUT:OUTSTD_LOGIC;F:OUTSTD_LOGIC_VECTOR(4DOWNTO1));ENDCOMPONENT;COMPONENTM4XORPORT(A:INSTD_LOGIC_VECTOR(4DOWNTO1);M:INSTD_LOGIC;B:OUTSTD_LOGIC_VECTOR(4DOWNTO1));ENDCOMPONENT;COMPONENTycpdPORT(a,b,c:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALX,TY:STD_LOGIC_VECTOR(4DOWNTO1);SIGNALCOUT:STD_LOGIC;BEGINU1:M4XORPORTmap(B,M,X);U2:add4PORTmap(A,X,M,cout,Ty);u3:ycpdportmap(a(4),x(4),TY(4),YC);Y=TY;ENDARCHITECTURErt1;910114.乘法电路程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_arith.ALL;USEIEEE.STD_LOGIC_unsigned.ALL;ENTITYmultISPORT(B,A:INSTD_LOGIC_VECTOR(4DOWNTO1);y:outSTD_LOGIC_VECTOR(8DOWNTO1));ENDENTITYmult;ARCHITECTURErt1OFmultIS12signalta:STD_LOGIC_VECTOR(8DOWNTO1);BEGINta=0000&a;Process(a,b,ta)variablety:STD_LOGIC_VECTOR(8DOWNTO1);beginty:=00000000;foriin1to4loopifb(i)='1'thenty:=ty+to_stdlogicvector(to_bitvector(ta)sll(i-1));--SLL左移左操作数必须是BIT_VECTOR，右操作数必须是INTEGER--先把TA转换为BIT_VECTOR，移位后再转换成stdlogicvector--ta移位后的值与TY相加，ta保持不变endif;endloop;y=ty;endprocess;ENDARCHITECTURErt1;13145.除法电路程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;15ENTITYdiv4ISgeneric(n:integer:=3);PORT(A,B:INintegerrange0to15;err:OUTSTD_LOGIC;y:OUTSTD_LOGIC_VECTOR(3DOWNTO0);rest:OUTintegerrange0to15);ENDENTITYdiv4;ARCHITECTURErt1OFdiv4ISBEGINPROCESS(a,b)VARIABLEAT,BT:integerrange0to15;BEGINAT:=A;BT:=B;ifb=0thenerr='1';elseerr='0';endif;FORIINndownto0LOOPifat=bt*2**itheny(i)='1';at:=at-b