7章+逻辑验证与Testbench+编写

TestbenchVerilog••Testbench•CPU•Testbench•Testbench•Verilog7.17.1.1SpecificationSPECRTLRTLLayout7-17-17Testbench1667-2RTLRTL7-2RTLRTLEDAEDAFPGA/CPLDModelSimRTLASICFPGA/CPLDModelSimActive-HDLHDLVerilog7.1.2TestbenchTestbenchTestbenchDUVDUTDUV7-31677-3TestbenchTestbenchEDACPLDHDLTestbenchTestbenchTestbench7-47-4TestbenchTestbenchnDUTDesignUnderTestnDUTnnEDATestbenchCodingStyle7Testbench168TestbenchRTLTestbench7.2TestbenchTestbenchtestbenchDUVcornercases7-5DUVDUV7-5MPI7.2.17.2.1.133.5.1testbenchDUVDUVtestbenchTestbench1697-67-67.2.1.2initialalwaysinitialalways2alwaysinitailinitialalwaysinitialalwaysinitialinitialwhilerepeatforforeverinitialbeginforever/**/begin……endendalwaysalways@(posedgeClock)beginSigA=SigB;…endClockalwaysbegin…end7.2.1.3Initial//10parameterFAST_PERIOD=10;7Testbench170regClock;initialbeginClock=0;forever#(FAST_PERIOD/2)Clock=~Clock;endalways//Always10parameterFAST_PERIOD=10;regClock;initialClock=0;//Clock0always#(FAST_PERIOD/2)Clock=~Clock;7-77-750%50always40//40parameterHi_Time=5,Lo_Time=10;regClock;alwaysbegin#Hi_TimeClock=0;#Lo_TimeClock=1;Testbench171end7-87-850%Clock0Clock5nsxinitialforeverinitailrepeat//2parameterPulseCount=4,FAST_PERIOD=10;regClock;initialbeginClock=0;repeat(PulseCount)#(FAST_PERIOD/2)Clock=~Clock;end2//parameterHI_TIME=5,LO_TIME=10,PHASE_SHIFT=2;regAbsolute_clock;//wireDerived_clock;//alwaysbegin7Testbench172#HI_TIMEAbsolute_clock=0;#LO_TIMEAbsolute_clock=1;Endassign#PHASE_SHIFTDerived_clock=Absolute_clock;alwaysAbsolute_clockassign2Derived_clock7-97-9AbsoluteclockderivedclockAbsolute_ClockregisterxDerived_clocknetzinitial//parameterPERIOD=10;regRst_n;initialbeginRst_n=1;#PERIODRst_n=0;#(5*PERIOD)Rst_n=1;endRst_n10ns50ns//initialbeginRst_n=1;@(negedgeClock);//Testbench173Rst_n=0;#30;@(negedgeClock);//Rst_n=1;end7-10Rst_n1Clock30ns7-10//initialbeginRst_n=1;@(negedgeClock);//Rst_n=0;//repeat(3)@(negedgeClock);//3Rst_n=1;//endRst_n1Clock33Rst_n7-117-117Testbench1747.2.1.4Verilog7-127-1224nsMY_ADDRMY_DATAinitial//ParameterSLOW_PERIOD=24;reg[5:0]Mpi_addr;regMpi_cs_n;regMpi_rw;regMpi_oe;tri[7:0]Mpi_data;reg[7:0]Data_out;assignMpi_data=(Mpi_oe)?Data_out:8'bz;initial//initialbeginMpi_addr=0;Mpi_cs_n=1;Mpi_rw=1;Mpi_oe=0;Data_out=0;#SLOW_PERIOD;Data_out=MY_DATA;Mpi_addr=MY_ADDR;Mpi_rw=0;#SLOW_PERIOD;Mpi_oe=1;#(SLOW_PERIOD/4);Testbench175Mpi_cs_n=0;#((2*SLOW_PERIOD)+(SLOW_PERIOD/2));Mpi_cs_n=1;#(SLOW_PERIOD/4);Mpi_addr=0;Mpi_rw=1;Mpi_oe=0;#SLOW_PERIOD;endMpi_datainitialMpi_datatriNet7.2.1.5testbenchdisplay$display(Addr:%b-DataWrite:%d,Mpi_addr,Data_out);$setup(Sig_D,posedgeClock,1);//Clock1nsSig_D$hold(posedgeClock,Sig_D,0.1);//Clock0.1nsSig_D$random()Data_out={$random}%256;//0~255$timetestbenchVerilog7.2.1.67Testbench176Verilogreg[7:0]DataSource[0:47];//$readmemh(Read_In_File.txt,DataSource);Read_In_FileDataSourceintegerWrite_Out_File;//Write_Out_File=$fopen(Write_Out_File.txt);//$fdisplay(Write_Out_File,@%h\n%h,Mpi_addr,Data_in);//$fclose(Write_Out_File);//7.2.1.7fork…join100ns//initialbegin100;fork//Send_task;Receive_task;joinend7.2.1.8ForforTestbench177initialbeginfor(i=0;im;i=i+1)//1m-1for(j=0;jn;j=j+1)//1n-1begincase(j)//0:Conf_Valuea;1:Conf_Valueb;2:Conf_Valuec;……endcase//endendVerilogfor7.2.1.9forcereleaseforcereleaseforce//forcereleasewirea;assigna=1'b0;initialbegin#10;forcea=1'b1;#10releasea;end10nsa0120nsa0forcereleaseVerilogXLforce01testbenchforceforce7Testbench1787.2.1.10CTestbenchTasktaskendtaskCPUtaskRead;output[7:0]Rtask_Data;//datareadoutinput[5:0]Rtask_Addr;beginuP_rw=0;#SLOW_PERIOD;uP_addr=Rtask_Addr;uP_rw=1;#SLOW_PERIOD;…endendtaskinputoutputtaskRead(Data,Addr);//AddrDataFunctionfunction[BITWIDTH–1:0]endfunctionBITWIDTHfunction[7:0]Product;input[3:0]Sig_A;input[3:0]Sig_B;Testbench179beginProduct=Sig_A*Sig_B;endendfunctionProductResult=Product(A,B);//ABProductResult7.2.1.11QuartusII7-137-13QuartusII7.2.2DUV33.5.17.2.1.1TestbenchDUV7-14Testbench7Testbench1807-14testbenchTestbenchTestbenchmoduleTestbench;////initialbegin…end//initialbegin…end//initialbegin…end//MPIu_MPI(.Clock(Clock),.Rst_n(Rst_n),.Mpi_data(Mpi_data),Testbench181.Mpi_addr(Mpi_addr),.Mpi_cs_n(Mpi_cs_n),.Mpi_rw(Mpi_rw));endmoduleVerilogTestbench7.4.67.2.3$display$monitor$fdisplay…nn3nGoldenVectorDatabasenGoldenWaveFile7Testbench182markerModelSimWaveComparenGoldenVector12127-15DUTTestVectorsDUTDUT7-15VCDVCDVCDVCD7-16VCDTestbench1837-16VCDVCD7.2.4Testbench7.2.4.1Testbenchtestbenchtestbenchtestbenchtestbench7.2.4.2TestbenchRTLTestbenchHDLTestbenchHDLHDL7-177Testbench1847-17HDLHDLHDLHDLnTestbenchTestbenchnPLI,ProgrammableLanguageInterfaceTestbenchCC++SystemVerilogSuperlogSystemCCoWareCCC++SystemVerilogSuperlogSystemCCoWareCTestbenchTestbenchn2nRTL32bit32BbitA*BCPU1857.2.4.3TestbenchTestbenchnTestbenchCPUMemoryforeveralwaysnTestbenchinitial,always,assign0nCPUMemorynCPURAMTestbench7.3CPUtestbenchtestbench7.3.17-18PowerPCFPGAFPGA7Testbench1867-18FPGAPowerPC7-197-197-207-20PowerPCPowerPCCPU187MPI7-18FPGA`timescale1ns/100psmoduleMPI(Clock,Rst_n,Mpi_data,Mpi_addr,Mpi_cs_n,Mpi_rw);inputClock;inputRst_n;i