JESD78D(Latch-Up)

JEDECSTANDARDICLatch-UpTestJESD78D(RevisionofJESD78C,September2010)NOVEMBER2011JEDECSOLIDSTATETECHNOLOGYASSOCIATIONNOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalcounsel.JEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationally.JEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocesses.BysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublications.TheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpoint.WithintheJEDECorganizationthereareprocedureswherebyaJEDECstandardorpublicationmaybefurtherprocessedandultimatelybecomeanANSIstandard.Noclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremet.Inquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orreferto©JEDECSolidStateTechnologyAssociation20113103North10thStreetSuite240SouthArlington,VA22201-2107Thisdocumentmaybedownloadedfreeofcharge;howeverJEDECretainsthecopyrightonthismaterial.Bydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterial.PRICE:ContactJEDECPrintedintheU.S.A.AllrightsreservedPLEASE!DON’TVIOLATETHELAW!ThisdocumentiscopyrightedbyJEDECandmaynotbereproducedwithoutpermission.Organizationsmayobtainpermissiontoreproducealimitednumberofcopiesthroughenteringintoalicenseagreement.Forinformation,contact:JEDECSolidStateTechnologyAssociation3103North10thStreetSuite240SouthArlington,VA22201-2107orreferto(ATE)53.3Heatsource54Procedure64.1Generallatch-uptestprocedure64.2Detailedlatch-uptestprocedure84.2.1I-test84.2.2Vsupplyovervoltagetest114.2.3Testingdynamicdevices124.2.4DUTdisposition124.2.5Recordkeeping135Latch-updetectioncriteria166Summary16Tables1Currentandvoltagetriggerconditions22TestMatrix73TimingspecificationsforI-testandVsupplyovervoltagetest8Figures1Latch-uptestflow62TestwaveformforpositiveI-test103TestwaveformfornegativeI-test104TestwaveformforVsupplyover-voltagetest125Theequivalentcircuitforpositiveinput/outputI-testlatch-uptesting136Theequivalentcircuitfornegativeinput/outputI-testlatch-uptesting147TheequivalentcircuitforVsupplyover-voltagetestlatch-uptesting15AnnexA(informative)Examplesofspecialpinsthatareconnectedtopassivecomponents17AnnexB(informative)CalculationofOperatingAmbientorOperatingCaseTemperatureforaGivenOperatingJunctionTemperature19AnnexC(informative)Examplesofrecordingandreportingdata20AnnexD(informative)Differencesbetweenrevisions21JEDECStandardNo.78D-ii-JEDECStandardNo.78DPage1ICLATCH-UPTEST(FromJEDECBoardBallotsJCB-96-69,JCB-08-45,JCB-10-34andJCB-11-81,formulatedunderthecognizanceofJC-14.1CommitteeonReliabilityTestMethodsforPackagedDevices.)1ScopeThisstandardcoverstheI-testandtheovervoltagelatch-uptestingofintegratedcircuits.ThepurposeofthisspecificationistoestablishamethodfordeterminingIClatch-upcharacteristicsandtodefinelatch-updetectioncriteria.Latch-upcharacteristicsareextremelyimportantindeterminingproductreliabilityandminimizingNoTroubleFound(NTF)andElectricalOverstress(EOS)failuresduetolatch-up.ThistestmethodisapplicabletoNMOS,CMOS,bipolar,andallvariationsandcombinationsofthesetechnologies.NOTEAsthesetechnologieshaveevolved,ithasbeennecessarytoadjustthisdocumenttotherealitiesofcharacterizationwithlimitsnotimaginedwhenthefirstlatch-updocumentwasgeneratedsome25yearsago.Thoughitwouldbesimplertomaketheoriginallimitsof1.5timesthemaximumpinoperatingvoltageanabsolutelevelofgoodness,thepossibilitiesofsuccessatthislevelarelimitedbytheverylowvoltagetechnologies,andthemediumandhighvoltageCMOS,BiCMOSandBipolartechnologies(40V).Theconceptofmaximumstressvoltage(MSV)allowsthesuppliertocharacterizelatch-upinawaythatdifferentiatesbetweenlatch-upandEOS.Thisrevisionwillmakeitmoretransparenttotheenduserthatgiventhelimitsofcertaintechnologiesthesubsequentlatch-upcharacterizationsarevalid.1.1ClassificationTherearetwoclassesforlatch-uptesting.ClassIisfortestingatroomtemperatureambient.ClassIIisfortestingatthemaximumoperatingambienttemperature(Ta)ormaximumoperatingcasetemperature(