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LearningObjectivesLesson4ExtractingandSimulatingTopologiesExtractatopologyfileusedforsingle-netanalysis.SimulateatopologyusingSigXplorer.UsetheSigWavewaveformmeasurementtool.CorrelateCadencereportedsimulationresultdatawithwaveformmeasurements.UsetheSigXplorersimulationfiles.TheAllegroPCBSIDesignFlowPre-PlacementSolutionSpaceAnalysisConstraint-DrivenFloorplanningConstraint-DrivenRoutingPost-RouteDRCPost-RouteAnalysisTheAllegroPCBSIDesignFlowconsistsofthefollowingsixsteps:EYouareHereDoubleClickHeretoOpentheImagePre-RouteExtractionSetup—DefaultModelSelectionFromtheAllegroPCBSImenuselectAnalyze—SI/EMISim—Preferences.DeterminesiftheDefaultIOCellmodelsaretobeused.DetermineswhichIOCellmodelistobeusedwhenthesimulatorencountersadriverorreceiverpinwithoutanassignedIOCellmodelOpenstheModelBrowsertoallowaccesstomodelscurrentlyloaded.DetermineshowthesimulatorobtainstheBufferDelay.Pre-RouteExtractionSetup—UnroutedInterconnectFromtheAllegroPCBSImenuselectAnalyze—SI/EMISim—Preferences.Setsthedefaultlengthforunroutedtransmissionlines.Setsthedefaultimpedancevalue.Setsthedefaultpropagationvelocityforunroutedtransmissionlines.Setsthedefaultdifferentialimpedanceforunroutedtransmissionlines.Setsthedefaultdifferentialvelocityforunroutedtransmissionlines.Pre-RouteTemplateExtractionFromtheAllegroPCBSImenuselectSetup—ElectricalConstraintSpreadsheet.TheXnetincludesthedrivers,receiversandinterconnectsofanextendednet.WhatarePhysicalNetsandXnetsElectricalNetsandPhysicalNets.Thissingleextendednet(Xnet)containstwophysicalnets.NetCLK0_1NetCLK0RLabUnroutedInterconnectExtractionSetupPre-LayoutTopologyExtractionforAnalysisSession-1SigXplorer610Pull-DownMenusSpreadsheetTabsNew,Open,SaveZoomfunctionsUndoNotesCanvasCleanupAccessModelBrowsertoaddanelementMove,Copy,Delete,Rotate,MirrorelementsSimulateUpdatecmHelpCommandConsoleModelIntegritySignalLibrarySigXplorerCommandTabSigXplorerParametersTabToggletodisplaytheunitsontheTLinetoLengthorTime.LengthTimeSigXplorerMeasurementsTabMeasurementsselectedwillhaveanXmarkinthecheckbox.SigXplorerResultsTabStartingSigXplorerSimulationAnalysisPreferences—PulseStimulusFromtheSigXplorermenuselectAnalyze—Preferences.Setthepulsenumbertomeasurefromaseriesofpulses.Setlaunchtimeoffsetbetweentheprimarydriverandneighbornetdrivers.AnalysisPreferences—SimulationParametersDefaultstimulusperiod100-----------------------------------------------=Default10ps20ps50ps100ps200ps500ps1ns2ns5ns10ns0.5ps1ps2ps5psFromtheSigXplorermenuselectAnalyze—Preferences.BandwidthforInterconnectParasiticstobesolvedbytheFieldSolver.FromLibraryOn-the-flyNoBufferDelayAnalysisPreferences—SimulationModesFromtheSigXplorermenuselectAnalyze—Preferences.Setsimulationspeedmode.ActiveDriverAllDriversAnalysisPreferences—MeasurementModesInputThresholdsVmeasAllSelectOneFromtheSigXplorermenuselectAnalyze—Preferences.ReflectionCrosstalkEMICheckthisboxtoobtaindelayanddistortionateachdriver.IOCellStimulusEditYouinvokethisformfromadriverintheSigXplorerworkspace.Usetheformtosetyourstimulusoptions.IOCellStimulusEdit(Continued)ClockDataEnableYouusethisformtosetyourcustomstimulusoptionsforIOCell.AsyncPeriodicSyncClockedLabSettingUpSimulationPreferencesandExecutingaReflectionSimulationSession-2WhatisSigWave?SigWavewindowcomponents:WaveformlibrarywindowEyeDiagramFFTModeBusModeCartesianModeSpreadsheetWaveformwindowMenuBarToolBarStatusBarSigWaveImportsandExportsTypesoffilesthatcanbeimportedintoSigWaveTypesoffilesthatcanbeexportedfromSigWaveSigWaveCurrentWaveformsSigWavewindowcomponents:WaveformlibrarywindowWaveformwindowMenuBarToolBarStatusBarSigWaveWaveformLibraryDelayMeasurements—RisingEdgePropagationDelayFinalSettleDelayFirstSwitchDelayVILMaxVIHMinRisingVmeasBufferDelayPropagationDelayPropagationDelayFirstSwitchDelayMaximumFlightTimeFinalSettleDelayMinimumFlightTimeDriverWaveformReceiverWaveformComponentThresholdsMeasurementThresholdBufferCadenceA.K.ATerminologyTranslationVoltageHighVoltageLowBufferDelayTimetoVrefBufferDelayWaveformDelayMeasurements—FallingEdgePropagationDelayFinalSettleDelayFirstSwitchDelayFallingVmeasBufferDelayDriverWaveformReceiverWaveformVILMaxVIHMinComponentThresholdsMeasurementThresholdBufferVoltageHighVoltageLowPropagationDelayPropagationDelayFirstSwitchDelayMaximumFlightTimeFinalSettleDelayMinimumFlightTimeCadenceA.K.ATerminologyTranslationBufferDelayTimetoVrefBufferDelayWaveformDelayMeasurements—OtherOvershootHighOvershootLowCadenceA.K.AOvershoot(RisingEdge)UndershootOvershoot(FallingEdge)OvershootTerminologyTranslationVILMaxVIHMinNoiseMarginHighNoiseMarginLowVoltageLowDelayMeasurements—MonotonicityDriverReceiverNon-monotonicedgereversalinmidrangeSomecausesofnon-monotonicedge:ExcessiveloadLargefanoutShorttraceswithimpedancediscontinuityVoltageLowVILMaxVIHMinComponentThresholdsDirectoriesandFilesCreatedfromSimulationsignoise.logsigxp.jrlinterconn.imldevices.dmlSigxp.dmlWorkingDirectorysigxp.runsignoise.cfgcasecases.cfgDirectoriesandFilesCreatedfromSimulationcase.cfgsigsimcntl.datprojstate.datcasesimsigsimres.datwaveformssim1.sims
本文标题:Cadence Allegro SI培训课件Lesson4
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