ACER 3620电路图AS3620_TM2420_Schematics_(Intel)

AABBCCDDEE44332211TitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01BLOCKDIAGRAMCustom140Friday,November11,2005CoreDesignTitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01BLOCKDIAGRAMCustom140Friday,November11,2005CoreDesignTitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01BLOCKDIAGRAMCustom140Friday,November11,2005CoreDesignAG1(Alviso)BlockDiagram2005/11/09CDROM20PATA2727LineOutDMII/FHOSTBUSDDRIIICH6-MLPCBUSPCIBUSIntel910GMLCLKGEN.IDTCV125400MHz100MHzKBCINT_KBTouchPad400MHzLVDSRGBBIOSROM4MBITS34,56,7,8,9,1011,1215,16,17,183129MDCCardG1421BCodecOPAMP27ACLINK2621MODEMMobileCPUALC65513CRTCONN14LCDUSB4PORTHDDMINIUSBBlue-toothDothanENEKB3910PM39LV040-70JCE303022,23LAN10/100RTL8110CL27LineInInt.MICIn28Mini-PCI802.11A/B/GDDRII400MHz11,12400MHz23TXFMPCMCIAONESLOTRJ45ENECB1410PWRSWCP221124,252525400MHz21INT.SPKRXGAG79219DCBATOUTINPUTSSYSTEMDC/DCTPS511203D3V_S53538OUTPUTSTPS51100DGQDDR_VREF5V_S5375V_S5CHARGER3D3V_S337DCBATOUT5V_S5INPUTSOUTPUTSSYSTEMDC/DCISL6227OUTPUTSINPUTSBT+ISL6255DCBATOUT16.8V3A27232120DDR_VREF_S3PCBLayerStackupL1:Signal1L2:VCCL3:Signal2L4:Signal3L5:GNDL6:Signal4PCB:05223-01ProjectCode:91.4G301.001XbusAPL5912-LACAPL5308-25ACINPUTSOUTPUTS5V_S53D3V_S02D5V_S01D5V_S03634ISL6218CV-TVCC_CORE0.844~1.3V27AOUTPUTSCPUDC/DCINPUTSDCBATOUTAABBCCDDEE44332211TitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01MemoA3240Tuesday,November01,2005CoreDesignTitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01MemoA3240Tuesday,November01,2005CoreDesignTitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01MemoA3240Tuesday,November01,2005CoreDesignAlvisoStrappingSignalsandConfigurationpage7ICH6internal20Kpull-upsapproximately33ohmDD[15:0],DDACK#,ICH6internal20Kpull-downsIORDY,LAN_RXD[2:0]ICH6-MIntegratedPull-upandPull-downResistorsICH6internal10Kpull-upsDCS3#,DCS1#,DIOR#,DREQ,DIOW#,ICH6-MEDS143080.8V1DA[2:0],ACZ_BIT_CLK,ACZ_RST#,ACZ_SDIN[2:0],ACZ_SYNC,ACZ_SDOUT,ACZ_BITCLK,USB[7:0][P,N]ICH6internal11.5Kpull-downsLAN_CLKDD[7],ICH6internal100Kpull-downsICH6-MIDEIntegratedSeriesTerminationResistorsSDDREQICH6internal15Kpull-downsDPRSLPVR,DPRSLP#,EE_DIN,EE_DOUT,EE_CS,GNT[5]#/GPO[17],GNT[6]#/GPO[16],LAD[3:0]#/FB[3:0]#,LDRQ[0],LDRQ[1]/GPI[41],PME#,PWRBTN#,SPKR,TP[3]IDEIRQMiniPCIIRQ252302FPCIRouting1410LAN1EREQ/GNTIDSEL21CFG[2:0]CFG[3:4]CFG5CFG6CFG7CFG[8:11]CFG[12:13]SDVOCRTL_DATAPinName001=FSB533010=FSB800DDRI/DDRIICFG17FSBFrequencySelect0=DMIx2CFG19011-111=ReversedReversed(Default)0=Prescott1=DothanCFG201=DMIx4StrapDescriptionDMIx2SelectCFG[14:15]CPUStrapReversedCFG16(Default)CFG18000=ReservedConfigurationXOR/ALLZteststraps00=ReservedReversed11=NormalOperation(Default)FSBDynamicODT0=DynamicODTDisabled10=AllZmodeenabled01=XORmodeenabled1=DynamicODTEnabled(Default)ReversedCPUcoreVCCSelectCPUVTTSelectReversedSDVOPresent0=1.05V1=1.5V(Default)1=1.2V0=1.05V(Default)(Default)1=SDVOdevicepresent0=NoSDVOdevicepresentNOTE:AllstrapsignalsaresampledwithrespecttotheleadingedgeoftheAlvisoGMCHPWORKInsignal.0=DDRII1=DDRIB.F.GFS_ACLK_PCIE_ICH#DREFSSCLK#DREFSSCLK3D3V_APWR_S03D3V_CLKGEN_S03D3V_48MPWR_S0CLK_CPU_BCLK1CLK_CPU_BCLK#1DREFSSCLK#1CLK_PCIE_ICH#1CLK_MCH_3GPLL1CLK_MCH_3GPLL#13D3V_CLKGEN_S0SS_SELDREFCLK#_1DREFCLK_1XTAL_INXTAL_OUTPCLK_MINIPCLK_KBCCLK48_ICHCLK_ICHPCIPCLK_PCMCLK_ICH14CLK_MCH_BCLKCLK_CPU_BCLKCLK_MCH_BCLK#CLK_CPU_BCLK#CLK_MCH_3GPLLDREFSSCLK1CLK_MCH_3GPLL#VTT_PWRGD#PCLK_LAN_1CLK_PCIE_ICHPCLK_KBC_1FS_APCLK_PCM_1SS_SELITP_ENCPU_SEL0CLK_PCIE_ICH13D3V_APWR_S0CLK_MCH_BCLK1CPU_SEL1CLK_MCH_BCLK#13D3V_48MPWR_S0ITP_ENPCLK_MINI_1VTT_PWRGD#DREFCLKDREFCLK#3D3V_CLKGEN_S03D3V_S03D3V_S03D3V_S03D3V_S0SMBD_ICH11,18CPU_SEL04,7PM_STPCPU#16,34CLK48_ICH16CLK_ICH1416CLK_ICHPCI16DREFCLK7DREFCLK#7PCLK_LAN22PCLK_MINI28PCLK_PCM24CLK_CPU_BCLK4CLK_CPU_BCLK#4CLK_MCH_3GPLL7CLK_MCH_3GPLL#7CLK_MCH_BCLK6CLK_MCH_BCLK#6CLK_PCIE_ICH16CLK_PCIE_ICH#16DREFSSCLK7DREFSSCLK#7PM_STPPCI#16SMBC_ICH11,186218_PGOOD32,34PCLK_KBC29CPU_SEL17CLK_Audio26TitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01ClockGenerator-IDT125A3340Friday,October28,2005CoreDesignTitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01ClockGenerator-IDT125A3340Friday,October28,2005CoreDesignTitleSizeDocumentNumberRevDate:SheetofWistronCorporation21F,88,Sec.1,HsinTaiWuRd.,Hsichih,TaipeiHsien221,Taiwan,R.O.C.AG1(Alviso)01ClockGenerator-IDT125A3340Friday,October28,2005CoreDesignH/L:100/96MHzH/L:CPU_ITP/SRC7EMIcapacitor001200M01Reserved01100MFS_B0133M111CPU000333MFS_C