Hardware Design of High Speed Switch Fabric IC

HardwareDesignofHighSpeedSwitchFabricICOverallArchitecture8x8TDMswitchSERTXIOSERTXIOSERTXIOSERTXIOSERTXIOSERTXIOSERTXIOSERTXIORXPLLTXPLLOverallArchitectureofthe8x8SwitchRXIODESERRXIODESERRXIODESERRXIODESERRXIODESERRXIODESERRXIODESERRXIODESERBypassFeatures•Supportsprotocol-independentswitching.Dataareencapsulatedinswitchingpacketsacrossthefabric.•Switchingpacketsizeis64bytes•Supports8x8switchwitheachportupto2.56~3.2Gbps•SupportsscalablemultichipswitchingFeatures•2.56~3.2GbpsI/O:--CMLIOdriver--EmbeddedSERDES--IntegratedCDRDeSerializerDeSerializer•ConvertstheCMLdifferentialinputtosinglebitinputdatathroughinputCMLbuffer•Convertsthesinglebitinputdataat2.56~3.2Gbpsrateinto16/20bitdatabusat160MHzclockrate•Inputreferenceclock160MHz•RXCML(clockmultiplyingunit)produces1.28-1.6GHzclockfordatarecoveryfromexternal160MHzclockDeSerializer•Inputreferenceclock160MHz•CDR(ClockDataRecovery)blockproduces1.28-1.6GHzclockfordatarecoveryfromexternal160MHzclockandinputdata•FrontEndreceiveruserecoveredclocktosampleandde-multiplexingsingleinputdatato4bitdatabusat640MHzclock•Use4to16/20DEMUXtoproduce16/20bitdatabusat160MHzDeSerializer•Commadetectortodetectcommawordtoaligndatabyteboundary•Use8/10bitdecodertodecodestartofpacket(SOP),destinationportanddata8x8TDMswitch8x8TDMswitch•PerformsthefirststageloadbalancedtrafficredistributionaftertheinputFIFOqueue•Inputtofirststageswitchisconsecutive64bytepacketateachinputport•Outputsoffirststageswitchincludedata,datavalid,destinationport,andsequenceID8x8TDMswitch•PerformsthesecondstageBirkhoff-von-Neumannswitchaftertheresequenceandoutputbufferqueue•Inputtosecondstageswitchisdistributivedatafromresequenceandoutputbufferqueue•Outputsofsecondstageswitchincludedata,startofpacket,anddestinationport8x8TDMswitch•Operatesat160MHzclockwithclockperiod6.2ns•For2.56Gbps(64bytes/packet)=5Mpackets/s•200ns/packetoperationtime(timeslot)=32cyclesfor160MHzSerializer•Performs16/20bencodingfunction•Paralleltoserialconversionconvert20/16bitdatabusat160MHztosinglebitoutputat2.56~3.2Gbps•DifferentialCMLoutputPLL•TXPLLtogenerate160MHzclockfordigitalcore•TXPLLtogeneratereference160MHzclockforsynthesizing1.28~1.6GHzclockforserializer•RXPLLtogenerate1.28~1.6GHzclockforCDRfromexternal160MHzclockTasks•PLLTR--PLL(TXandRX)designandHspicesimulation•DESER--DeSerializer(CDR)designandHspicesimulation•SWH-8x8TDMswitchdesign,synthesis,placeandroute,andverification•CCODEC--Commadetectand8/10bdecoder,8/10bencoderTasks•SERCML—SerializerandCMLhighspeedIObufferdesignandHspicesimulation•APRD—AnalogcustomizedlayoutforDERSER•APRS--AnalogcustomizedlayoutforSERanddriver•Fullchipintegrationandverification•Architecturespecs