《VHDL实用教程》完整版【汉语版】-8第六章

KONXINKONXIN6VHDL1316VHDLVHDLVHDL6-1VHDL6-1hConcurrentSignalAssignmentsh(ProcessStatements)h(BlockStatements)6-1VHDL132h(SelectedSignalAssignmentsh(ComponentInstantiations)h(GenerateStatements)h(ConcurrentProcedureCalls)ARCHITECTUREOFISBEGINENDARCHITECTUREVHDL§6.1VHDLVHDLVHDLVHDLKONXINKONXIN6VHDL133IFWAIT6-14in1(3DOWNTO0)1out1(3DOWNTO0)16-1LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcnt10ISPORTclr:INSTD_LOGIC;in1:INSTD_LOGIC_VECTOR(3DOWNTO0);out1:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDcnt10ARCHITECTUREactvOFcnt10ISBEGINPROCESSin1clrBEGINIF(clr='1'ORin1=1001)THENout1=0000;--9out10ELSE--1out1=in1+1;--++ENDIF--STD_LOGIC_UNSIGNEDENDPROCESS;ENDactv;6-16-2ADDER14A(3DOWNTO0)+B0=S(3DOWNTO0)B0=1MUX426-26-211ADDER41A0A1A2A3B0S0S1S2S3MUX42A0A1A2A3B0B1B2B3S0Z0Z1Z2Z3out1[0]in1[0]out1[1]in1[1]out1[2]in1[2]out1[3]in1[3]VCCclrADDEROR2NOTAND4S0=0:=Z[3..0]=A[3..0)S0=1:=Z[3..0]=B[3..0]106-26-1cnt10VHDL1346-26-1WAIT6-36-2LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcnt10ISPORT(clr:INSTD_LOGIC;Clk:INSTD_LOGIC;Cnt:BufferSTD_LOGIC_VECTOR(3DOWNTO0));ENDcnt10ARCHITECTUREactvOFcnt10ISBEGINPROCESSBEGINWAITUNTILclk'EVENTANDclk='1';--clkIF(clr='1'ORcnt=9)THENcnt=0000;ELSEcnt=cnt+1;ENDIF;ENDPROCESS;ENDactv;6-26-36-24D1ADDER41A0A1A2A3B0S0S1S2S3MUX42A0A1A2A3B0B1B2B3S0Z0Z1Z2Z3FD11D0Q0FD11D0Q0FD11D0Q0FD11D0Q0out1[0]out1[1]out1[2]VCCclrout1[3]clkADDEROR2NOTAND4S0=0:=Z[3..0]=A[3..0)S0=1:=Z[3..0]=B[3..0]106-3cnt10(4D)KONXINKONXIN6VHDL13544DBUFFER6-34rsts0clkcurrent_statecurrent_state6-46-3PACKAGEmtypeISTYPEstate_tIS(s0,s1,s2,s3);--ENDmtype;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEWORK.mtype.ALL;--ENTITYs4_machineISPORT(clk,inc,a1,b1:INSTD_LOGIC;rst:INBOOLEAN;out1:OUTSTD_LOGIC);ENDENTITYs4_machine;ARCHITECTUREactivOFs4_machineISSIGNALcurrent_state,next_state:state_t;BEGINsync:PROCESS(clk,rst)--BEGINIF(rst)THEN--current_state=s0;ELSIF(clk’EVENTANDclk='1')THEN--current_state=next_state;ENDIF;ENDPROCESSsync;fsm:PROCESS(inccurrent_state,a1,b1)--BEGINout1=a1;CDQCDQABSb1a1incout1clkrstNAND3NOR2NOTNAND2D_FFMUX216-44VHDL136next_state=s0;IF(inc='1')THENCASEcurrent_stateISWHENs0=next_state=s1;WHENs1=next_state=s2;out1=b1;WHENs2=next_state=s3;WHENs3=NULL;ENDCASE;ENDIF;ENDPROCESSfsm;ENDactiv;6-43336-4...a_out=aWHEN(ena)ELSE'Z';b_out=bWHEN(enb)ELSE'Z';c_out=cWHEN(enc)ELSE'Z';PRO1PROCESS(a_out)BEGINbus_out=a_out;ENDPROCESS;PRO2PROCESS(b_out)BEGINbus_out=b_out;ENDPROCESS;PRO3PROCESS(c_out)BEGINbus_out=c_out;ENDPROCESS;...36-599-309-31OT11OT11OT11bus_outenaenbencabca_outc_outb_out6-56-4KONXINKONXIN6VHDL137§6.26-56-5...b1:BLOCK--b1SIGNALs:BIT;--b1sBEGINs=aANDb;--b1sb2:BLOCK--b2b1SIGNALs:BIT;--b2sBEGINs=cANDd;--b2sb3:BLOCKBEGINz=s;--sb2ENDBLOCKb3;ENDBLOCKb2;y=s;--sb1ENDBLOCKb1;6-623aybczd6-62VHDL138§6.3hhh6.3.1VHDL=6-66-6ARCHITECTUREcurtOFbc1ISSIGNALs1:STD_LOGIC;BEGINoutput1=aANDb;output2=c+d;B1:BLOCKSIGNALe,f,g,h:STD_LOGIC;BEGINg=eORf;h=eXORf;ENDBLOCKB1s1=g;ENDARCHITECTUREcurt6.3.2KONXINKONXIN6VHDL139=WHENELSEWHENELSE...IF=TRUEIFELSEWHENCASE5-95-26-76-7...z=aWHENp1='1'ELSEbWHENp2='1'ELSEc;...p1p21za6.3.3WITHSELECT=WHENWHEN...WHENCASECASECASEWITHCASEVHDL1406-86-7abcdata1data2dataout6-8LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYdecoderISPORT(abc:INSTD_LOGIC;data1data2:INSTD_LOGIC;dataout:OUTSTD_LOGIC);ENDdecoder;ARCHITECTUREconcuntOFdecoderISSIGNALinstruction:STD_LOGIC_VECTOR(2DOWNTO0)BEGINinstruction=c&b&a;WITHinstructionSELECTdataout=data1ANDdata2WHEN000data1ORdata2WHEN001data1NANDdata2WHEN010data1NORdata2WHEN011data1XORdata2WHEN100data1XNORdata2WHEN101'Z'WHENOTHERS;ENDconcunt;6-9416-9...WITHseltSELECTmuxout=aWHEN0|1,--01bWHEN2TO5,--2345DECODERabcd1d2d_outabcdataoutdata1data26-76-8DECODERKONXINKONXIN6VHDL141cWHEN6,dWHEN7,'Z'WHENOTHERS;...§6.46-106-10...PROCEDUREadder(SIGNALa,b:INSTD_LOGIC;--adderSIGNALsum:OUTSTD_LOGIC);...adder(a1b1sum1);--...--a1b1sum1absumPROCESS(c1c2);--BEGINAdder(c1c2s1);--c1c2s1ENDPROCESS;--absum106-11check1checkerrorTRUE6-11PROCEDUREcheck(SIGNALa:INSTD_LOGIC_VECTOR;--SIGNALerror:OUTBOOLEAN)IS--VARIABLEfound_one:BOOLEAN:=FALSE;--BEGINFORiINa'RANGELOOP--aIFa(i)='1'THEN--a'1'IFfound_oneTHEN--found_oneTRUE'1'ERROR=TRUE;--'1'found_oneTRUEVHDL142RETURN;--ENDIF;Found_one:=TRUE;--a'1'EndIF;EndLOOP;--aerror=NOTfound_one;--'1'errorTRUEENDPROCEDUREcheck6-12...CHBLKBLOCKSIGNALs1:STD_LOGIC_VECTOR(0TO0);--SIGNALs2:STD_LOGIC_VECTOR(0TO1);SIGNALs3:STD_LOGIC_VECTOR(0TO2);SIGNALs4:STD_LOGIC_VECTOR(0TO3);SIGNALe1,e2,e3,e4:Boolean;BEGINCheck(s1,e1);--s1e1Check(s2,e2);--s2e2Check(s3,e3);--s3e3Check(s4,e4);--s4e4ENDBLOCK;...6-8s2[1]e2s2[0]s3[0]s3[2]s3[1]e3s4[0]s4[1]e4s4[2]s4[3]s1[0]e16-8CHBLKKONXINKONXIN6VHDL143§6.5VHDLVHDLFPGAVerilogIPFPGAIPCOMPONENTISGENERIC--PORTENDCOMPONENTPORTMAP--[=]...PORTMAPVHDL144=PORTMAPPORTMAP6-13/1426-936-136-136-13LIBRARYIEEEUSEIEEE.STD_LOGIC_1164.ALLENTITYnd2ISPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDnd2;ARCHITECTUREnd2behvOFnd2ISBEGINy=aNANDb;ENDnd2behv;6-14LIBRARYIEEEUSEIEEE.STD_LOGIC_1164.AL