《VHDL实用教程》完整版【汉语版】-11第九章

KONXINKONXIN91719VHDLSynthesisVHDLFPGA/CPLDASICEDAVHDLVHDLVHDLVHDLVHDLVHDL1616PLD1VHDLVHDLVHDL§9.1VHDLEDAVHDLVHDL//VHDL172VHDLVHDLSpeedAreaDensityVHDLVHDLVHDLVHDLVHDLVHDLVHDLVHDLVHDLEDAVHDLVHDLFPGA/CPLDEDAMAX+PLUSIIHDLHDL/VHDLKONXINKONXIN9173VHDLVHDLVHDLVHDLVHDLVHDLIEEEEDAVHDLVHDLEDAEDASynopsysDesignCompilerFPGAExpressFPGACompilerIISynplicitySynplifyCandenceSynergyMentorGraphicsAutologicIIDATAI/OSynarioViewlogicWorkviewOfficeAlteraMAX+plusIIVHDLFPGAExpressSynopsysFPGA/CPLDVHDL/VerilogFPGA/CPLDFPGA/CPLDVHDLEDIFEDIFEDAPLDEDAEDIF200VHDLADDER4.VHDFPGAExpressispLSI1032ExportEDIFADDER4.EDFLatticeISPDS+FPGA/CPLDEDIFEDAVHDLEDIFVCCGNDMAX+plusIIEDIFEDALatticeISPDS+5.0AlteraEDIFMAX+plusIILatticeMAX+plusIIEDAEDIFLatticeEDAAlteraFPGAExpressSynplifyEDIFWorkviewOfficeEDIFVHDLVHDLVHDL174§9.2VHDLVHDLVHDLVHDLVHDLVHDLVHDLVHDLVHDL32VHDLVHDLVHDLVHDL/CPLDFPGAVHDLEDAKONXINKONXIN9175§9.3VHDLVHDL1WAITIFhhIF_THENIF_THEN_ELSEhhIFIFhIFTruehIFELSEELSIF9.3.1(1)9-19-1PROCESS(clk_a,clk_b)BEGINIF(clk_a'EVENTANDclk_a='1')THENa=b;VHDL176ENDIF;IF(clk_b'EVENTANDclk_b='1')THEN--c=b;ENDIF;ENDPROCESS;(2)9-2ELSE9-2PROCESS(clock)BEGINIF(clock'EVENTANDclock='1')THENsig=b;ELSEsig=c;--ENDIF;ENDPROCESS;ELSEsig=c;(3)IF9-39-3PROCESS(clock)VARIABLEedge_var,any_var:BIT;BEGINIF(clock'EVENTANDclock='1')THENedge_signal=x;--edge_var:=y;--any_var:=edge_var;--ENDIF;any_var:=edge_var;--ENDPROCESS;(4)IFNOT(clock'EVENTANDclock='1')THEN...(5)9-4IFELSEgatedata9-4PROCESS(gate,data)BEGINIF(gate='1')THENq=data;ENDIF;ENDPROCESS;KONXINKONXIN9177(6)9-59-5FUNCTIONmy_func(data,gate:BIT)RETURNBITISVARIABLEs1:BIT;BEGINIF(gate='1')THENs1:=data;ENDIF;RETURNs1;END;...q=my_func(data,gate);...(7)9-6IBAH9-19-6LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYEXAPISPORT(CLK,C,J,K:INSTD_LOGIC;A,H:OUTSTD_LOGIC);ENDEXAP;ARCHITECTUREbehavOFEXAPISSIGNALI,B:STD_LOGIC;BEGINPROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENB=C;A=B;H=I;I=JXORK;ENDIF;ENDPROCESS;ENDbehav;9-79-29-7LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYEXAPISPORT(CLK,C,J,K:INSTD_LOGIC;A,H:OUTSTD_LOGIC);ENDEXAP;VHDL178ARCHITECTUREbehavOFEXAPISSIGNALI,B:STD_LOGIC;BEGINPROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENB=C;I=JXORK;ENDIF;ENDPROCESS;A=B;H=I;ENDbehav;(8)9-89-8x='1';IFx='1'x9-89-39-8LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYEXAPISPORT(clk,a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDEXAP;ARCHITECTUREbehavOFEXAPISSIGNALx:STD_LOGIC;BEGINPROCESSBEGINWAITUNTILCLK='1';x='0';y='0';IFa=bTHENx='1';DQDQDQDQDQDQJJHHKKCLKCACACLKAHABHI9-19-69-29-7KONXINKONXIN9179ENDIF;IFx='1'THENy='1';ENDIF;ENDPROCESS;ENDbehav;9-8xx9-49-9LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYEXAPISPORT(clk,a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDEXAP;ARCHITECTUREbehavOFEXAPISBEGINPROCESSVARIABLEx:STD_LOGIC;BEGINWAITUNTILCLK='1';x:='0';y='0';IFa=bTHENx:='1';ENDIF;IFx='1'THENy='1';ENDIF;ENDPROCESS;ENDbehav;DQDQDQaayybbCLKCLKa=ba=b9-39-89-49-9VHDL1809.3.2IF_THENWAITPROCESS(clk)BEGINIFclk='1'THENy=a;ELSE--VHDLENDIF;ENDPROCESS;yyABEL-HDLABEL-HDLELSE09-109-10PROCESS(clk)BEGINIFclk='1'THENy=a;ELSEy=b;ENDIF;ENDPROCESS;9-1021IFIFCASE9-11PROCESS(clk)BEGINIFclk='1'THEN----ELSEy=a;ENDIF;ENDPROCESS;9-12PROCESS(clk)BEGINIFclk='0'THENKONXINKONXIN9181y=a;--ENDIF;ENDPROCESS;9-13clk'EVENTANDclk='1'9-13PROCESS(clk)BEGINIFclk'EVENTANDclk='1'THENy=a;ENDIF;ENDPROCESS;9-14STD_LOGICrising_edge()9-14SIGNALclkSTD-LOGIC...PROCESS(clk)BEGINIFrising_edge(clk)THENy=a;ENDIF;ENDPROCESS;WAIT9-15WAITayy9-15PROCESSWAITUNTILclk'EVENTANDclk='1'y=a;ENDPROCESS;VHDLWAITWAIT9-16IF9-16PROCESS(clk,a,b)BEGINIFclk='1'THENy=aANDb;ENDIF;ENDPROCESS;VHDL1829-17IF9-17ARCHITECTUREdataflowOFlatchISPROCEDUREmy_latch(SIGNALclk,a,b:INBoolean;SIGNALy:OUTBoolean)BEGINIFclk='1'THENy=aANDb;ENDIF;END;BEGINLatch_1:my_latch(clock,input1,input2,outputa);Label_2:my_latch(clock,input1,input2,outputb);ENDdataflow;9-18Y9-18LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYEXAPISPORT(b,a:INSTD_LOGIC;clk:BOOLEAN;Y1:OUTSTD_LOGIC);ENDEXAP;ARCHITECTUREbehavOFEXAPISSIGNALY:STD_LOGIC;BEGINY=aANDbWHENclkELSEY;Y1=Y;ENDbehav;clk='1'ANDclk'EVENT9-199-18ELSE9-199-59-18KONXINKONXIN9183ARCHITECTUREconcurrentOFmy_registerISBEGINY=aANDbWHENclk='1'ANDclk'EVENT;ENDconcurrent;9-181076-1993VHDL1076-19879.3.39-209-69-20LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYEXAPISPORT(clk,d:INSTD_LOGIC;ena:INBOOLEAN;--enaq1:OUTSTD_LOGIC);ENDEXAP;ARCHITECTUREbehavOFEXAPISSIGNALq:STD_LOGIC;BEGINPROCESS(clk,ena)BEGINIF(clk='1'ANDclk'EVENT)ANDenaTHENq=d;ENDIF;q1=q;ENDPROCESS;ENDbehav;9-219-21IFclk='1'ANDclk'EVENTTHENIFenaTHEN--ena9-69-20VHDL184q=d;ENDIF;ENDIF;9.3.49-229-79-22PROCESS(clk)BEGINIFclk='1'ANDclk'EVENTTHENIFset='1'THENy='1';--'1'TRUEELSEy=aANDb;ENDIF;ENDIF;ENDPROCESS;set/reset/reset='0'FALSEyTRUE/FALSE/9.3.59-79-229-89-23KONXINKONXIN9185VHDL//PLD9-239-23--BOOLEANLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYEXAPISPORT(clk,reset:INSTD_LOGIC;a,b:INBOOLEAN;Y1OUTBOOLEAN);ENDEXAP;ARCHITECTUREbehavOFEXAPISSIGNALY:BOOLEAN;BEGINPROCESS(clk,reset)BEGINIFreset='1'THENy=FALSE;ELSIFclk='1'ANDclk'EVENTTHENy=aANDb;ENDIF;ENDPROCESS;Y1=Y;ENDbehav;VH