东南大学计算结构POC报告

ComputerOrganizationandArchitectureCOURSEDESIGNNAMESTUDENTNUMBERCOURSEComputerOrganizationandArchitectureCourseDesignPROJECTAParallelOutputControllerBasingOnVerilogHDLSOFTWAREPLATFORMISE14.1DATEMAR.17.20141.Purpose(1)Todesignandsimulateaparalleloutputcontroller(POC)whichactsaninterfacebetweensystembusandprinter.(2)TheuseofISEsoftwarefordesignandsimulation.2.Tasks(1)POCisoneofthemostcommonI/Omodules,namelytheparalleloutputcontroller.Itplaystheroleofaninterfacebetweenthecomputersystembusandtheperipheral(suchasaprinterorotheroutputdevices).Figure1PrinterConnectionFigureshowstheconnectingofaprintertothesystembusthroughthePOC.(2)ThecommunicationbetweenPOCandtheprinteriscontrolledbya“handshake”protocolillustratedinFigure.Figure2Thehandshake-timingdiagrambetweenPOCandtheprinterThehandshakingprocessisdescribedasfollows:Whentheprinterisreadytoreceiveacharacter,itholdsRDY=1.ThePOCmustthenholdacharacteratPD(paralleldata)portandproduceapulseattheterminalTR(transferrequest).TheprinterwillchangeRDYto0,takethecharacteratPDandholdtheRDYat0untilthecharacterhasbeenprinted(e.g.5or10ms),thensetRDY=1againwhenitisreadytoreceivethenextcharacter.(Supposetheprinterhasonlyaonecharacter“buffer”register,sothateachcharactermustbeprintedbeforethenextcharacterissent).(3)ThebufferregisterBRisusedtoholdacharacterthathasbeensentviathesystembuswhilethatthecharacterisbeingtransferredtotheprinter.ThestatusregisterSRisusedfortwocontrolfunctions:SR7servesasareadyflagforsystembustransferstoBR(liketheprinterRDYsignalfortransfersfromPOCtotheprinter),andSR0isusedtoenableordisableinterruptrequestsfromPOC.IfSR0=1,thenPOCwillinterruptwhenitisreadytoreceiveacharacter(i.e.,whenSR7=1).IfSR0=0,thenPOCwillnotinterrupt.TheotherbitsofSRarenotusedandempty.(4)ThetransferofacharactertoPOCviathesystembusproceedsasfollows.Inpollingmode,SR0isalways0.TheprocessorselectsSRbyaccessingtherelativeaddress,thenreadsSRregister,ifSR7=1,theprocessorselectsBRandwritesacharacterintoBR,thenprocessorclearsSR7toindicatethatthenewcharacterhasbeenwrittenintoBRandnotprintedyet.WhenPOCdetectsthatSR7issetto0,POCthenproceedstostartthehandshakingoperationswiththeprinter.Aftersendingcharactertoprinter,POCsetstheSR7to1,whichindicatesPOCisreadytoreceiveanothercharacterfromtheprocessor.Thetransfercyclecannowrepeat.DuringthehandshakingoperationsbetweenPOCandprinter,theprocessorcontinuestofetchandexecuteinstructions.IfithappenstoreadSR,itwillfindSR7=0andhencewillnotattempttosendanothercharactertothePOC.Ininterruptmode,SR0isalways1.Aftersendingcharactertoprinter,POCsetstheSR7to1,sinceSR0=1,theinterruptrequestsignal(IRQ)issetto0,whichindicateaneffectiveinterruptsignaltotheprocessor.WhentheprocessordetectstheeffectiveIRQsignal,theprocessordirectlyselectsBRandwritesacharacterintoBR,andthentheprocessorsetstheSR7to0,whichindicatesthatthenewcharacterhasbeenwrittenintoBRandnotprintedyet.WhenPOCdetectsthatSR7issetto0,POCthenproceedstostartthehandshakingoperationswiththeprinter.Aftersendingcharactertoprinter,POCsetstheSR7to1,whichindicatesPOCisreadytoreceiveanothercharacterfromtheprocessor.Thetransfercyclecannowrepeat.DuringthehandshakingoperationsbetweenPOCandprinter,theprocessordoesnottrytoaccessPOCuntilitreceivestheinterruptrequestsignal.3.TheoverallconnectionexpressedinthetopmoduleformFigure3TheoverallconnectionexpressedinthetopmoduleformInordertobeeasytodebug,someinsidesignalsandregistersaresetasoutputsignals.Infact,wejustonlyneedclk,clk2,reset,csandPDtobeoutsidesignals.SignalsorregistersFunctionclkClockofCPUandPOCclk2ClockofPrinterresetResetwhenreset=0cscs=0:pollingmode;cs=1:interruptmodePDDatatobeprintedTable1Theexplicationoftheoutsidesignals4.DesigndescriptionofthesimulationinputwaveformsAsisshownintable1，4simulationinputsignalsareneeded.(1)clkClockofCPUandPOC.(2)clk2ClockofPrinter,fasterthanclk.(3)resetResetwhenreset=0.(4)cscs=0:pollingmode;cs=1:interruptmode.5.Simulationresults(1)Inpollingmode,cs=0,SR0isalways0.(2)Ininterruptmode,cs=1,SR0isalways1.6.ConclusionsandDiscussionsPOC,paralleloutputcontroller,playsaroleasaninterfacebetweenCPUandtheprinter.Asisshownabove,thetwosimulationwavesrevealthatthisdesignmeetstherequirements.Inmydesign,allthecodesaremyoriginalworks.IhavewrittenthemoduleProcessortohelpcompletingsimulation,whichneedmorecodesanddebuggingtocooperatewiththeworkofPOC.EventhereisalreadyaschematicforthemodulePrinterintheteachingmaterial,IstillhavetodomoreworktofinishthismodulebecausethesoftwareIuseisISEwhosedevicesisdifferentfromthoseofQuartusII.Theprocedureofdesignhelpsmeunderstandtheworkingprincipleofinterface.InthethirdtermofGrade2didwelearnsomethingaboutcomputerinterfaceinthecourseMicrocomputer.AndthecourseCOAhasreferredtoit,too.HereIusewhatIhavelearnedtodesignthisprogramandachievealot.Inthisprogram,IusetheEDAsoftwareISEandVeriloghardwarelanguagetodesignthosethreemodulesandIsim,whichisamoduleofISE,andVHDLlanguageforsimulation.Asaresult,Ibecomemorefamiliarwiththeuseofhardwaredescriptionlanguage.Appendix------------------------------CPU------------------------------modulePOC_CPU(out