CD4051BEE4中文资料

1DatasheetacquiredfromHarrisSemiconductorSCHS047GCAUTION:Thesedevicesaresensitivetoelectrostaticdischarge;followproperICHandlingProcedures.Copyright©2003,TexasInstrumentsIncorporatedCD4051B,CD4052B,CD4053BFeatures•WideRangeofDigitalandAnalogSignalLevels-Digital..............................3Vto20V-Analog...............................≤20VP-P•LowONResistance,125Ω(Typ)Over15VP-PSignalInputRangeforVDD-VEE=18V•HighOFFResistance,ChannelLeakageof±100pA(Typ)atVDD-VEE=18V•Logic-LevelConversionforDigitalAddressingSignalsof3Vto20V(VDD-VSS=3Vto20V)toSwitchAnalogSignalsto20VP-P(VDD-VEE=20V)•MatchedSwitchCharacteristics,rON=5Ω(Typ)forVDD-VEE=15V•VeryLowQuiescentPowerDissipationUnderAllDigital-ControlInputandSupplyConditions,0.2µW(Typ)atVDD-VSS=VDD-VEE=10V•BinaryAddressDecodingonChip•5V,10V,and15VParametricRatings•100%TestedforQuiescentCurrentat20V•MaximumInputCurrentof1µAat18VOverFullPackageTemperatureRange,100nAat18Vand25oC•Break-Before-MakeSwitchingEliminatesChannelOverlapApplications•AnalogandDigitalMultiplexingandDemultiplexing•A/DandD/AConversion•SignalGatingCMOSAnalogMultiplexers/DemultiplexerswithLogicLevelConversionTheCD4051B,CD4052B,andCD4053Banalogmultiplexersaredigitally-controlledanalogswitcheshavinglowONimpedanceandverylowOFFleakagecurrent.Controlofanalogsignalsupto20VP-Pcanbeachievedbydigitalsignalamplitudesof4.5Vto20V(ifVDD-VSS=3V,aVDD-VEEofupto13Vcanbecontrolled;forVDD-VEEleveldifferencesabove13V,aVDD-VSSofatleast4.5Visrequired).Forexample,ifVDD=+4.5V,VSS=0V,andVEE=-13.5V,analogsignalsfrom-13.5Vto+4.5Vcanbecontrolledbydigitalinputsof0Vto5V.ThesemultiplexercircuitsdissipateextremelylowquiescentpoweroverthefullVDD-VSSandVDD-VEEsupply-voltageranges,independentofthelogicstateofthecontrolsignals.Whenalogic“1”ispresentattheinhibitinputterminal,allchannelsareoff.TheCD4051Bisasingle8-Channelmultiplexerhavingthreebinarycontrolinputs,A,B,andC,andaninhibitinput.Thethreebinarysignalsselect1of8channelstobeturnedon,andconnectoneofthe8inputstotheoutput.TheCD4052Bisadifferential4-Channelmultiplexerhavingtwobinarycontrolinputs,AandB,andaninhibitinput.Thetwobinaryinputsignalsselect1of4pairsofchannelstobeturnedonandconnecttheanaloginputstotheoutputs.TheCD4053Bisatriple2-Channelmultiplexerhavingthreeseparatedigitalcontrolinputs,A,B,andC,andaninhibitinput.Eachcontrolinputselectsoneofapairofchannelswhichareconnectedinasingle-pole,double-throwconfiguration.Whenthesedevicesareusedasdemultiplexers,the“CHANNELIN/OUT”terminalsaretheoutputsandthe“COMMONOUT/IN”terminalsaretheinputs.NOTE:Whenordering,usetheentirepartnumber.Thesuffixes96andRdenotetapeandreel.ThesuffixTdenotesasmall-quantityreelof250.OrderingInformationPARTNUMBERTEMP.RANGE(oC)PACKAGECD4051BF3A,CD4052BF3A,CD4053BF3A-55to12516LdCERAMICDIPCD4051BE,CD4052BE,CD4053BE-55to12516LdPDIPCD4051BM,CD4051BMT,CD4051BM96CD4052BM,CD4052BMT,CD4052BM96CD4053BM,CD4053BMT,CD4053BM96-55to12516LdSOICCD4051BNSR,CD4052BNSR,CD4053BNSR-55to12516LdSOPCD4051BPW,CD4051BPWR,CD4052BPW,CD4052BPWRCD4053BPW,CD4053BPWR-55to12516LdTSSOPAugust1998-RevisedOctober2003[/Title(CD4051B,CD4052B,CD4053B)/Sub-ject(CMOSAnalogMulti-plex-ers/Demultiplex-erswithLogicLevelConver-sion)/Author()/Key-words(HarrisSemi-conduc-tor,CD40002PinoutsCD4051B(PDIP,CDIP,SOIC,SOP,TSSOP)TOPVIEWCD4052B(PDIP,CDIP,SOP,TSSOP)TOPVIEWCD4053B(PDIP,CDIP,SOP,TSSOP)TOPVIEW1415169131211101234576846COMOUT/IN75INHVSSVEEVDD103ABC2CHANNELSIN/OUTCHANNELSIN/OUTCHANNELSIN/OUT1415169131211101234576802COMMON“Y”OUT/IN31INHVSSVEEVDD1COMMON“X”OUT/IN03AB2YCHANNELSIN/OUTYCHANNELSIN/OUTXCHANNELSIN/OUTXCHANNELSIN/OUT14151691312111012345768bybxcyOUT/INCXORCYIN/OUTCXINHVSSVEEVDDOUT/INaxORayayaxABCOUT/INbxORbyIN/OUTIN/OUTFunctionalBlockDiagramsCD4051B111096A†B†C†INH†134251121514TGTGTGTGTGTGTGTG3COMMONOUT/IN01234567BINARYTO1OF8DECODERWITHINHIBITLOGICLEVELCONVERSION87VSSVEE16VDDCHANNELIN/OUT†AllinputsareprotectedbystandardCMOSprotectionnetwork.CD4051B,CD4052B,CD4053B3CD4052BCD4053BFunctionalBlockDiagrams(Continued)1211151401233210XCHANNELSIN/OUTYCHANNELSIN/OUTBINARYTO1OF4DECODERWITHINHIBIT133COMMONYOUT/INCOMMONXOUT/IN78166910A†B†INH†VSSVEEVDDTGTGTGTGTGTGTGTG4251LOGICLEVELCONVERSION111096A†B†C†INH†12351213TGTGTGTGTGTG4COMMONOUT/INaxaybxbycxcy87VSSVEE16VDDIN/OUT1514BINARYTO1OF2DECODERSWITHINHIBITLOGICLEVELCONVERSIONVDD†AllinputsareprotectedbystandardCMOSprotectionnetwork.COMMONOUT/INCOMMONOUT/INaxORaybxORbycxORcyCD4051B,CD4052B,CD4053B4TRUTHTABLESINPUTSTATES“ON”CHANNEL(S)INHIBITCBACD4051B00000000110010200113010040101501106011171XXXNoneCD4052BINHIBITBA0000x,0y0011x,1y0102x,2y0113x,3y1XXNoneCD4053BINHIBITAORBORC00axorbxorcx01ayorbyorcy1XNoneX=Don’tCareCD4051B,CD4052B,CD4053B5AbsoluteMaximumRatingsThermalInformationSupplyVoltage(V+toV-)VoltagesReferencedtoVSSTerminal...........-0.5Vto20VDCInputVoltageRange..................-0.5VtoVDD+0.5VDCInputCurrent,AnyOneInput......................±10mAOperatingConditionsTemperatureRange.........................-55oCto125oCPackageThermalImpedance,θJA(seeNote1):E(PDIP)package...............................67oC/WM(SOIC)package...........