20重庆大学EDA课程设计 EDA课程设计-vhdl语言-12.24小时时钟-乐曲播放电路-函数信号

附录一、12/24小时数字时钟VHDL设计1，系统顶层逻辑图：时序仿真波形管脚定义以及锁定2，分频模块。①各个分频模块的模块图：②，分别对应的仿真波形：③50mhz分频至1k模块代码：libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;entitywh4574_divto1kisport(clk50m:instd_logic;clk1k:outstd_logic);endwh4574_divto1k;architecturebehavofwh4574_divto1kissignalcount1:std_logic_vector(14downto0);signalcount2:std_logic;signalco:std_logic;beginprocess(clk50m)beginifclk50m'eventandclk50m='1'thenifcount1=110000110100111thencount1=000000000000000;co='1';elsecount1=count1+'1';co='0';endif;endif;endprocess;process(co)beginifco'eventandco='1'thencount2=notcount2;endif;endprocess;clk1k=count2;endbehav;50mhz分频至2k模块代码：libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;entitywh4574_divto2kisport(clk50m:instd_logic;clk2k:outstd_logic);endwh4574_divto2k;architecturebehavofwh4574_divto2kissignalcount1:std_logic_vector(13downto0);signalcount2:std_logic;signalco:std_logic;beginprocess(clk50m)beginifclk50m'eventandclk50m='1'thenifcount1=11000011010011thencount1=00000000000000;co='1';elsecount1=count1+'1';co='0';endif;endif;endprocess;process(co)beginifco'eventandco='1'thencount2=notcount2;endif;endprocess;clk2k=count2;endbehav;1k分频至5hz代码：libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;entitywh4574_div1kto5isport(inclk1k:instd_logic;clk5hz:outstd_logic);endwh4574_div1kto5;architecturebehavofwh4574_div1kto5issignalcount1:std_logic_vector(6downto0);signalcount2:std_logic;signalco:std_logic;beginprocess(inclk1k)beginifinclk1k'eventandinclk1k='1'thenifcount1=1100011thencount1=0000000;co='1';elsecount1=count1+'1';co='0';endif;endif;endprocess;process(co)beginifco'eventandco='1'thencount2=notcount2;endif;endprocess;clk5hz=count2;endbehav;5分频代码：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitywh4574_div_5isport(clk:instd_logic;q:outstd_logic);endwh4574_div_5;architecturebehavofwh4574_div_5issignalcount:std_logic_vector(2downto0);beginprocess(clk)beginifclk'eventandclk='1'thenifcount=100thencount=000;q='1';elsecount=count+1;q='0';endif;endif;endprocess;endbehav;3，按键去抖动模块，二选一模块。①模块图：②时序仿真波形依次为：③源代码：按键去抖动：libraryieee;useieee.std_logic_unsigned.all;useieee.std_logic_1164.all;entitywh4574_qudouisport(clk,keyin:instd_logic;keyout:outstd_logic);endwh4574_qudou;architecturebehavofwh4574_qudouisbeginprocess(clk)variablecount1,count2:std_logic_vector(3downto0);beginifclk'eventandclk='1'thenifkeyin='0'thenifcount1=0101thenkeyout='0';elsecount1:=count1+1;endif;elsifkeyin='1'thenifcount2=0101thenkeyout='1';elsecount2:=count2+1;endif;endif;endif;endprocess;endbehav;二选一数选器：libraryieee;useieee.std_logic_1164.all;entitywh4574_T_mux2isport(sel,a,b:instd_logic;q:outstd_logic);endwh4574_T_mux2;architecturebavofwh4574_T_mux2isbeginprocess(sel,a,b)beginifsel='1'thenq=a;elseq=b;endif;endprocess;endbav;4，24,60进制计数器模块，24小时转12小时模块，动态译码显示模块。①模块图：②时序仿真波形图。24进制计数波形：60进制仿真波形：24小时制转12小时制：③，程序源代码.24进制计数器：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitywh4574_count24isport(CLK:instd_logic;bcd10,bcd1:bufferstd_logic_vector(3downto0);CO:OUTSTD_LOGIC);endwh4574_count24;architecturebehavofwh4574_count24isbeginprocess(CLK,bcd10)beginifCLK'EVENTANDCLK='1'THENifbcd10=0010andbcd1=0011thenbcd1=0000;CO='1';elsifbcd1=1001thenbcd1=0000;CO='0';elsebcd1=bcd1+'1';CO='0';endif;endif;endprocess;process(CLK,bcd1)beginifCLK'eventandCLK='1'thenifbcd1=0011andbcd10=0010thenbcd10=0000;elsifbcd1=1001thenbcd10=bcd10+'1';endif;endif;endprocess;endbehav;60进制：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitywh4574_count60isport(clk:instd_logic;bcd10,bcd1:bufferstd_logic_vector(3downto0);preset:instd_logic;co:outstd_logic);endwh4574_count60;architecturertlofwh4574_count60issignalco_1:std_logic;beginprocess(clk,preset)beginifpreset='0'thenbcd1=0000;elseifclk='1'andclk'eventthenifbcd1=1001thenbcd1=0000;elsebcd1=bcd1+'1';endif;endif;endif;endprocess;process(clk,preset,bcd1)beginifpreset='0'thenbcd10=0000;co_1='0';elseifclk='1'andclk'eventthenifbcd1=1000andbcd10=0101thenco_1='1';elsifbcd1=1001andbcd10=0101thenbcd10=0000;co_1='0';elsifbcd1=1001thenbcd10=bcd10+'1';co_1='0';endif;endif;endif;endprocess;co=notco_1;endrtl;24转换12libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitywh4574_transisport(clk:instd_logic;switchP:instd_logic;T24_10,T24_1:instd_logic_vector(3downto0);T12_10,T12_1:bufferstd_logic_vector(3downto0));endwh4574_trans;architecturebehavofwh4574_transisbeginprocess(T24_10,T24_1)begincaseswitchP&T24_10&T24_1iswhen100000000=T12_10=0000;T12_1=0000;when100000001=T12_10=0000;T12_1=0001;when100000010=T12_10=0000;T12_1=0010;when100000011=T12_10=0000;T12_1=0011;when100000100=T12_10=0000;T12_1=0100;when100000101=T12_10=0000;T12_1=0101;when100000110=T12_10=0000;T12_1=0110;when100000111=T12_10=0000;T12_1=0111;when100001000=T12_10=0000;T12_1=1000;when100001001=T12_10=0000;T12_1=1001;when100010000=T12_10=0001;T12_1=0000;when100010001=T12_10=0001;T12_1