Simulation and Synthesis Techniques for Asynchrono

ExpertVerilog,SystemVerilog&SynthesisTrainingSimulationandSynthesisTechniquesforAsynchronousFIFODesignCliffordE.Cummings,SunburstDesign,[e-mail]usedtosafelypassdatafromoneclockdomaintoanotherasynchronousclockdomain.UsingaFIFOtopassdatafromoneclockdomaintoanotherclockdomainrequiresmulti-asynchronousclockdesigntechniques.TherearemanywaystodesignaFIFOwrong.TherearemanywaystodesignaFIFOrightbutstillmakeitdifficulttoproperlysynthesizeandanalyzethedesign.Thispaperwilldetailonemethodthatisusedtodesign,synthesizeandanalyzeasafeFIFObetweendifferentclockdomainsusingGraycodepointersthataresynchronizedintoadifferentclockdomainbeforetestingforFIFOfullorFIFOemptyconditions.Thefullycoded,synthesizedandanalyzedRTLVerilogmodel(FIFOStyle#1)isincluded.Post-SNUGEditorialCommentAsecondFIFOpaperbythesameauthorwasvoted“BestPaper-1stPlace”bySNUGattendees,islistedasreference[3]andisalsoavailablefordownload.SNUGSanJose2002SimulationandSynthesisTechniquesforRev1.2AsynchronousFIFODesign21.0IntroductionAnasynchronousFIFOreferstoaFIFOdesignwheredatavaluesarewrittentoaFIFObufferfromoneclockdomainandthedatavaluesarereadfromthesameFIFObufferfromanotherclockdomain,wherethetwoclockdomainsareasynchronoustoeachother.AsynchronousFIFOsareusedtosafelypassdatafromoneclockdomaintoanotherclockdomain.TherearemanywaystodoasynchronousFIFOdesign,includingmanywrongways.MostincorrectlyimplementedFIFOdesignsstillfunctionproperly90%ofthetime.Mostalmost-correctFIFOdesignsfunctionproperly99%+ofthetime.Unfortunately,FIFOsthatworkproperly99%+ofthetimehavedesignflawsthatareusuallythemostdifficulttodetectanddebug(ifyouareluckyenoughtonoticethebugbeforeshippingtheproduct),orthemostcostlytodiagnoseandrecall(ifthebugisnotdiscovereduntiltheproductisinthehandsofadissatisfiedcustomer).ThispaperdiscussesoneFIFOdesignstyleandimportantdetailsthatmustbeconsideredwhendoingasynchronousFIFOdesign.Therestofthepapersimplyreferstoan“asynchronousFIFO”asjust“FIFO.”2.0PassingmultipleasynchronoussignalsAttemptingtosynchronizemultiplechangingsignalsfromoneclockdomainintoanewclockdomainandinsuringthatallchangingsignalsaresynchronizedtothesameclockcycleinthenewclockdomainhasbeenshowntobeproblematic[1].FIFOsareusedindesignstosafelypassmulti-bitdatawordsfromoneclockdomaintoanother.DatawordsareplacedintoaFIFObuffermemoryarraybycontrolsignalsinoneclockdomain,andthedatawordsareremovedfromanotherportofthesameFIFObuffermemoryarraybycontrolsignalsfromasecondclockdomain.Conceptually,thetaskofdesigningaFIFOwiththeseassumptionsseemstobeeasy.ThedifficultyassociatedwithdoingFIFOdesignisrelatedtogeneratingtheFIFOpointersandfindingareliablewaytodeterminefullandemptystatusontheFIFO.2.1SynchronousFIFOpointersForsynchronousFIFOdesign(aFIFOwherewritesto,andreadsfromtheFIFObufferareconductedinthesameclockdomain),oneimplementationcountsthenumberofwritesto,andreadsfromtheFIFObuffertoincrement(onFIFOwritebutnoread),decrement(onFIFOreadbutnowrite)orhold(nowritesandreads,orsimultaneouswriteandreadoperation)thecurrentfillvalueoftheFIFObuffer.TheFIFOisfullwhentheFIFOcounterreachesapredeterminedfullvalueandtheFIFOisemptywhentheFIFOcounteriszero.Unfortunately,forasynchronousFIFOdesign,theincrement-decrementFIFOfillcountercannotbeused,becausetwodifferentandasynchronousclockswouldberequiredtocontrolthecounter.TodeterminefullandemptystatusforanasynchronousFIFOdesign,thewriteandreadpointerswillhavetobecompared.2.2AsynchronousFIFOpointersInordertounderstandFIFOdesign,oneneedstounderstandhowtheFIFOpointerswork.Thewritepointeralwayspointstothenextwordtobewritten;therefore,onreset,bothpointersaresettozero,whichalsohappenstobethenextFIFOwordlocationtobewritten.OnaFIFO-writeoperation,thememorylocationthatispointedtobythewritepointeriswritten,andthenthewritepointerisincrementedtopointtothenextlocationtobewritten.Similarly,thereadpointeralwayspointstothecurrentFIFOwordtoberead.Againonreset,bothpointersareresettozero,theFIFOisemptyandthereadpointerispointingtoinvaliddata(becausetheFIFOisemptyandtheemptyflagisasserted).AssoonasthefirstdatawordiswrittentotheFIFO,thewritepointerincrements,theemptyflagiscleared,andthereadpointerthatisstilladdressingthecontentsofthefirstFIFOmemoryword,immediatelydrivesthatfirstvalidwordontotheFIFOdataoutputport,tobereadbythereceiverlogic.ThefactthatthereadpointerisalwayspointingtothenextFIFOwordtobereadmeansthatthereceiverlogicdoesnothavetousetwoclockperiodstoreadthedataword.IfthereceiverfirsthadtoincrementthereadpointerbeforereadingaFIFOdataSNUGSanJose2002SimulationandSynthesisTechniquesforRev1.2AsynchronousFIFODesign3word,thereceiverwouldclockoncetooutputthedatawordfromtheFIFO,andclockasecondtimetocapturethedatawordintothereceiver.Thatwouldbeneedlesslyinefficient.TheFIFOisemptywhenthereadandwritepointersarebothequal.Thisconditionhappenswhenbothpointersareresettozeroduringaresetoperation,orwhenthereadpointercatchesuptothewritepointer,havingreadthelastwordfromtheFIFO.AFIFOisfullwhenthepointersareagainequal,thatis,whenthewritepointerhaswrappedaroundandcaugh