LayoutGuide_DDR3

ISSIDDR3SDRAMLayoutGuildRevision0A.May4,2012.IntroductionThisisageneralPCBlayoutguidelineforISSIDDR3SDRAM,especiallytargetingforpointtopointapplication.ChipsetcompaniesmayrequireforaspecialoradditionalguidelineforDDR3.ISSIrecommendsfollowingthechipsetcompany’srulefirst.PCBLayoutGuidelinesFR-4iscommonlyusedforthedielectricmaterial.Anditsthicknessandtracewidthandthicknessshouldbeadjustedformatchingtheimpedance.Tracelengthsarealsoimportantthatshouldbedeterminedthroughsimulationforeachsignalgroup.Ingeneral,ISSIrecommendstheminimumrulesfortraceinPCBasbelowforthecrosstalk.Theserulesarebasedontheassumptionofsignalslewrateof1V/1ns.Inslowerapplication,crosstalkissuewouldbelessandcloserspacingmaybeallowed.1.Signalsfromthesamenetgroupshouldberoutedonthesamelayer.2.SignalsfromBytegroup,suchasDQS,DMand8bitsofDQ,mustberoutedinthesamelayer3.Thedeviationofsignalpropagationdelayisdependentonthetimingbudgetontheapplication.Followingvalueinthetableisagoodexampleforthebeginningofdesign.SignalsonNetMaximumdeviationofsignalpropagationdifference.Maximumdeviationoftracelength.Betweensignalswithinbytegroup(DQS,DM,8bitsofDQ)±10ps±1.270mm(50mil)Betweensignalswithinaddressnet.Betweensignalswithincommandsnet.Betweenonebytegroupandanotherbytegroup.±50ps±6.635mm(261mil)BetweenCKandCK#.BetweenDQSnandDQS#n±2ps±0.254mm(10mil)Betweenoneclockpairandanotherclockpair,eg)CK/CK#andDQSn/DQS#n±5ps±0.635mm(25mil)4.Minimumtracewidthis0.13mm(5mil).5.Intranetspacing,thedistancebetweentwoadjacenttraceswithinanet,is0.2mm(7mil).6.Internetspacing,thedistancebetweenthetwooutermostsignalsofdifferentsignalgroupis15mil.Sameruleappliesbetweenoneclockpairandanotherclockpair.7.Differentialclocksshouldberoutedinparallelandkeepthetracelengthshort.8.Differentialclocksmustberoutedonthesamelayerandplacedonaninternallayerminimizethenoise.9.KeepsomedistancebetweenCKEandCK/CK#VREFcontrolSetupandholdtimemarginwillbereducedwhenVREFhasanoise.VREFshouldbedesignedbytheusertoprovideoptimumnoisemargininthesystem.VREFisexpectedtotrackvariationsinVDDQandthepicktopicknoiseshouldbemetwithspecification.1.1KΩ±1%/1KΩ±1%/fromVDDQpowerpanel.2.Placea0.1uFcapacitorbetweenVREFandVDDQ3.Placea0.1uFcapacitorbetweenVREFandVSSQ4.VREFshouldhaveaminimumtracetoreduceinductance.5.VREFshouldhaveawidetrace.Min20milisrecommended.6.VREFshouldkeepadistancefromothersignalstoreducedecouplingeffect.Atleast,25milisrecommended.EMIandtermination.TheDDR3SDRAMusesaprogrammableimpedanceoutputbuffer.Theoutputdrivestrengthiscalibratedduringinitialization.Andthisfeatureminimizesanyprocessvariationpresentinthedriver.Tocalibrateoutputdriverimpedance,RZQneedstobelocatedbetweentheZQballandVSSQ.ThevalueofRZQmustbe240Ω±1%.RZQcan’tbeshared.EachDDR3shouldhaveitsownRZQ.Thedrivestrengthsettingisselectedbyprogrammingthememorymoderegistersettingdefinedbymoderegister1(MR1).AndthedefaultstrengthisRZQ/6(=40Ω).Inlayout,theimpedanceforallsingleendeddatagroupshouldbecloseto40Ωandthatfordifferentialshouldbecloseto80Ω.RefertothedesignguidelinesofDRAMcontrollervendorforthedetailrestrictionandrecommendation.DDR3SDRAMalsointroducesanewfeature“DynamicODT”andallowsdifferentODTsettingdependingontheoperationstate.Thisfeatureincreasesflexibilitytooptimizeterminationvaluesfordifferentloadingconditions.However,theresultofenablingthisfeaturecanbedifferentdependinghowODTofDRAMcontrollerbehavior.UsershouldfollowDRAMcontrollerguideline.LANDpatternFollowIPC-SM-782A,keepsizeoflandpatterntobeequalto80%oftheballsizeofBGA.Foranyquestions,pleasecontactthefollowingindividualsfromISSI’sapplication.AndersonZhang([e-mail]),JiffLee([e-mail]),JihoKim([e-mail])