DELL-N4110主板电路图

1122334455667788AABBCCDDSizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:BLOCKDIAGRAM1AWednesday,January19,2011V02A/RO1A161SizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:BLOCKDIAGRAM1AWednesday,January19,2011V02A/RO1A161SizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:BLOCKDIAGRAM1AWednesday,January19,2011V02A/RO1A161PCI-EPAGE27LEVELSHIFTERUSB[0]USB2.01366x768(HD)INTHDMIUSB[8]CardReaderPAGE30RTL5128-GRiGFXInterfacesLPCKBCITE8518PAGE45PWMFAN&ThermalCPUSandyBridge35WPAGE32SPIROMPAGE41DMILINKPAGE4~8PAGE9~15PAGE42PCHCougerPointLAYER6:IN3PAGE55DGFX_COREPAGE49ChargerPAGE503/5V1.05V_VTT/PCHPAGE53PAGE56CPU_COREPAGE511.5V_SUS/0.75V_DDR1.8V_RUNPAGE52VCCSAPAGE54WhistlerLP(128bit)29mmX29mmBGA969SPIROMPAGE414MB512KBPAGE313-axisFallSensorSMBUSUSB[11]USB[5]USB[4]USB[2]LAYER7:GNDLAYER8:BOTDISPCBSTACKUPODDSATA16G/SPAGE3625mmX25mmBGA98932.768KHz25MHz8LH=4mmLAYER2:GNDLAYER4:VCCLAYER1:TOPLAYER3:IN1HM67KeyboardConn.PAGE42LAYER5:IN22.5GT/sE-SATASATA43G/SPAGE28PAGE31SATA06G/SSATA-HDDPGA988CameraPAGE30HDMICONNPAGE27SPI2.5GT/sPAGE34WLANPAGE35WWANDDRIII-SODIMM1DDRIII1333MT/sPAGE16FDILINKH=8mmPAGE17DDRIII1333MT/sDDRIII-SODIMM2CRTBoardPAGE26INTCRTLCDCONNPAGE25INTSingleCHANNELLVDSATIPCIEx16SeymourXT(64bit)PAGE18~22DDR32GB128Mx16bitx8PG23,24MobileIntelSeries6ChipsetV02A/R01ADISBLOCKDIAGRAMTouchPadIOBoardPCI-EPAGE38PAGE38PAGE37USB3.0Portsx2PCIE[5]USB3.0ControllerPAGE36PCIE[2]PCIE[1]PCIE[3]X2IHDAAudioCodecALC269PAGE3825MHzRealtekLANPAGE39RTL8111ELRJ45PAGE39PAGE38JackSpeakerDigital-MICIHDAPAGE33USBPortx1PAGE29PAGE35ESATA+USB2.0MBSideRobsonXT(64bit)1122334455667788AABBCCDDSizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:PowerRails1AWednesday,January19,2011V02A/RO1A261SizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:PowerRails1AWednesday,January19,2011V02A/RO1A261SizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:PowerRails1AWednesday,January19,2011V02A/RO1A261powerStateS0S1S3S4/S5ACS4/S5DCOnlyAC/DCNoExistSMBDATASMBCLKSMB_CLK_ME1SMB_DAT_ME1AB1A_DATAAB1A_CLK5544332211DDCCBBAASizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:BLANK1AWednesday,January19,2011V02A/RO1A361SizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:BLANK1AWednesday,January19,2011V02A/RO1A361SizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:BLANK1AWednesday,January19,2011V02A/RO1A3615544332211DDCCBBAAPEG_COMPeDP_COMPINT_eDP_HPDPEG_RXN12PEG_TXP1_CPEG_TXP2_CPEG_TXP3_CPEG_TXP4_CPEG_TXP5_CPEG_TXP6_CPEG_TXP7_CPEG_TXP0_CPEG_TXP8_CPEG_TXP9_CPEG_TXP10_CPEG_TXP11_CPEG_TXP12_CPEG_TXP13_CPEG_TXP14_CPEG_TXP15_CPEG_RXN13PEG_TXP9PEG_TXP14PEG_TXP0PEG_TXP3PEG_TXP4PEG_TXP15PEG_RXN14PEG_RXN15PEG_TXN1_CPEG_TXN1PEG_TXN4PEG_TXN6PEG_TXN9PEG_TXN10PEG_TXN11PEG_TXN12PEG_TXN2_CPEG_TXN3_CPEG_TXN4_CPEG_RXN1PEG_TXN5_CPEG_RXP12PEG_RXP13PEG_RXP14PEG_RXP15PEG_RXP1PEG_RXP2PEG_RXP3PEG_RXP0PEG_RXP4PEG_RXP5PEG_RXP6PEG_RXP7PEG_RXP8PEG_RXP9PEG_RXP10PEG_RXP11PEG_TXN6_CPEG_RXN2PEG_TXN7_CPEG_RXN3PEG_TXN0_CPEG_RXN0PEG_TXN8_CPEG_RXN4PEG_TXN9_CPEG_RXN5PEG_TXN10_CPEG_RXN6PEG_TXN11_CPEG_RXN7PEG_TXN12_CPEG_RXN8PEG_TXN13_CPEG_RXN9PEG_TXN14_CPEG_RXN10PEG_TXN15_CPEG_RXN11PEG_TXP6PEG_TXP8PEG_TXP1PEG_TXN14PEG_TXP5PEG_TXP7PEG_TXN15PEG_TXP11PEG_TXN8PEG_TXN2PEG_TXP2PEG_TXN5PEG_TXN13PEG_TXP12PEG_TXN3PEG_TXN0PEG_TXP10PEG_TXP13PEG_TXN7eDP_COMPINT_eDP_HPDPEG_COMPDMI_TXN09DMI_TXN19DMI_TXN29DMI_TXN39DMI_TXP09DMI_TXP19DMI_TXP29DMI_TXP39DMI_RXN09DMI_RXN19DMI_RXN29DMI_RXN39DMI_RXP09DMI_RXP19DMI_RXP29DMI_RXP39FDI_TXN09FDI_TXN19FDI_TXN39FDI_TXN29FDI_TXN59FDI_TXN79FDI_TXN69FDI_TXN49FDI_TXP19FDI_TXP59FDI_TXP79FDI_TXP69FDI_TXP49FDI_TXP39FDI_TXP29FDI_TXP09FDI_FSYNC09FDI_FSYNC19FDI_INT9FDI_LSYNC19FDI_LSYNC09PEG_TXN[0..15]18PEG_TXP[0..15]18PEG_RXN[0..15]18PEG_RXP[0..15]18+1.05V_PCH+1.05V_PCH+1.05V_PCHSizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:SandyBridge1/51AWednesday,January19,2011V02A/RO1A461SizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:SandyBridge1/51AWednesday,January19,2011V02A/RO1A461SizeDocumentNumberRevDate:SheetofQuantaComputerInc.PROJECT:SandyBridge1/51AWednesday,January19,2011V02A/RO1A461SandyBridgeProcessor(DMI,PEG,FDI)DP&PEGCompensationPEG_ICOMPIandRCOMPOsignalsshouldberoutedwithin500milsPEG_ICOMPOsignalsshouldberoutedwithin500milseDP_COMPIOandICOMPOsignalsshouldbeshortednearballsandroutedwithin500milseDP_ICOMPO12mileDP_COMPIO4milPEG_ICOMPO12milPEG_ICOMPI,PEG_RCOMPO4mil,ProgramingDisableeDPinterface(BIOS)eDPHot-plug(Disable)ThissignalcanbeleftasnoconnectifentireeDPinterfaceisdisabled.CADNote:PlacePUresistorwithin2inchesofCPU0.22uFACcouplingCapsforPCIEGEN1/2/3C420.1U/10V_4C420.1U/10V_4C270.1U/10V_4C270.1U/10V_4C4770.1U/10V_4C4770.1U/10V_4C4880.1U/10V_4C4880.1U/10V_4C470.1U/10V_4C470.1U/10V_4C380.1U/10V_4C380.1U/10V_4C320.1U/10V_4C320.1U/10V_4C400.1U/10V_4C400.1U/10V_4C520.1U/10V_4C520.1U/10V_4R20*10K_4_NCR20*10K_4_NCC4700.1U/10V_4C4700.1U/10V_4C4820.1U/10V_4C4820.1U/10V_4C450.1U/10V_4C450.1U/10V_4C290.1U/10V_4C290.1U/10V_4C460.1U/10V_4C460.1U/10V_4R2124.9/F_4R2124.9/F_4C440.1U/10V_4C440.1U/10V_4C250.1U/10V_4C250.1U/10V_4R