S3C44B0 中文手册

1S3C44B0X16/32RISCS3C44B0X2.5VARM7TDMI8Kcache;internalSRAM;LCDController(256STNLCDDMA)2-chUARTwithhandshake(IrDA1.0,16-byteFIFO)/1-chSIO2-chgeneralDMAs/2-chperipheralDMAswithexternalrequestpinsExternalmemorycontroller(chipselectlogic,FP/EDO/SDRAMcontroller)5-chPWMtimers&1-chinternaltimerWatchDogTimer71generalpurposeI/Oports/8-chexternalinterruptsourceRTCwithcalendarfunction8-ch10-bitADC1-chmulti-masterIIC-BUScontroller1-chIIS-BUScontrollerSync.SIOinterfaceandOn-chipclockgeneratorwithPLL.S3C44B0XARMCPU-SAMBA266MHZNormal,Slow,Idle,andStopmode1Little/Bigendiansupport.2Addressspace:32Mbytespereachbank.(Total256Mbyte)3Supportsprogrammable8/16/32-bitdatabuswidthforeachbank.4Fixedbankstartaddressandprogrammablebanksizefor7banks.5.8memorybanks.-6memorybanksforROM,SRAMetc.-2memorybanksforROM/SRAM/DRAM(FastPage,EDO,andSynchronousDRAM)6.FullyProgrammableaccesscyclesforallmemorybanks.7Supportsexternalwaitsignaltoexpendthebuscycle.8.Supportsself-refreshmodeinDRAM/SDRAMforpower-down.9.Supportsasymmetric/symmetricaddressofDRAM.Cache:•4-waysetassociativeID(Unified)-cachewith8Kbyte.•The0/4/8KbytesinternalSRAMusingunusedcachememory.•PseudoLRU(LeastRecentlyUsed)ReplaceAlgorithm.•Writethroughpolicytomaintainthecoherencebetweenmainmemoryandcachecontent.•Writebufferwithfourdepth.•Requestdatafirstfilltechniquewhencachemissoccurs.•Lowpower•Theon-chipPLLmakestheclockforoperatingMCUatmaximum66MHz.•Clockcanbefedselectivelytoeachfunctionblockbysoftware.•Powermode:Normal,Slow,IdleandStopmode.Normalmode:Normaloperatingmode.Slowmode:LowfrequencyclockwithoutPLLIdlemode:StoptheclockforonlyCPUStopmode:Allclocksarestopped•WakeupbyEINT[7:0]orRTCalarminterruptfromidlemode.•30Interruptsources(Watch-dogtimer,6Timer,6UART,8Externalinterrupts,4DMA,2RTC,1ADC,1IIC,1SIO)•VectoredIRQinterruptmodetoreduceinterruptlatency.•Level/edgemodeontheexternalinterruptsources•Programmablepolarityofedgeandlevel•SupportsFIQ(FastInterruptrequest)forveryurgentinterruptrequest•5-ch16-bitTimerwithPWM/1-ch16-bitinternaltimerwithDMA-basedorinterrupt-basedoperation•Programmabledutycycle,frequency,andpolarity•Dead-zonegeneration.•Supportsexternalclocksource.RTC:•Fullclockfeature:msec,sec,min,hour,day,week,month,year.•32.768KHzoperation.•AlarminterruptforCPUwake-up.•Timetickinterrupt:•8externalinterruptports•71multiplexedinput/outputportsUART:•2-channelUARTwithDMA-basedorinterrupt-basedoperation•Supports5-bit,6-bit,7-bit,or8-bitserialdatatransmit/receive•SupportsH/Whandshakingduringtransmit/receive•Programmablebaudrate•SupportsIrDA1.0(115.2kbps)•Loopbackmodefortesting•Eachchannelhavetwointernal32-byteFIFOforRxandTx.DMA:•2channelgeneralpurposeDirectMemoryAccesscontrollerwithoutCPUintervention.•2channelBridgeDMA(peripheralDMA)controller.•SupportIOtomemory,memorytoIO,IOtoIOwiththeBridgeDMAwhichhas6type'sDMArequestor:Software,4internalfunctionblocks(UART,SIO,Timer,IIS),andExternalpins.•ProgrammablepriorityorderbetweenDMAs(fixedorround-robinmode)•BursttransfermodetoenhancethetransferrateontheFPDRAM,EDODRAMandSDRAM.•Supportsfly-bymodeonthememorytoexternaldeviceandexternaldevicetomemorytransfermodeA/D:•8-chmultiplexedADC.•Max.100KSPS/10-bit.LCD:•Supportscolor/monochrome/grayLCDpanel•Supportssinglescananddualscandisplays•Supportsvirtualscreenfunction•Systemmemoryisusedasdisplaymemory•DedicatedDMAforfetchingimagedatafromsystemmemory•Programmablescreensize•Graylevel:16graylevels•256Colorlevels:•16-bitWatchdogTimer•Interruptrequestorsystemresetattime-outIIC-BUS•1-chMulti-MasterIIC-Buswithinterrupt-basedoperation.•Serial,8-bitoriented,bi-directionaldatatransferscanbemadeatupto100Kbit/sinthestandardmodeorupto400Kbit/sinthefastmode.IIS-BUS•1-chIIS-busforaudiointerfacewithDMA-basedoperation.•Serial,8/16bitperchanneldatatransfers•SupportsMSB-justifieddataformatSIO():•1-chSIOwithDMA-basedorinterrupt–basedoperation.•Programmablebaudrates.•Supportsserialdatatransmit/receiveoperations8-bitinSIO.:•:2.5VI/O:3.0Vto3.6V:•Upto66MHz:•160LQFP/160FBGA2om[1:0]:om[1:0]S3C44B0XnGCS0,.00:8-bit01:16-bit10:32-bit11:TestmodeADDR[24:0]:.DATA[31:0]:,8/16/32nGCS[7:0]:,..nWE:,.nWBE[3:0]:nBE[3:0]:SRAM.nOE:,.nXBREQ:nXBREQnXBACKnXBACKnWAITnWAITnWAITENDIANlittleendianbigendian.0:littleendian1:bigendiannRAS[1:0]nCAS[3:0]nSRASSDRAMnSCASSDRAMnSCS[1:0]SDRAMDQM[3:0]SDRAMSCLKSDRAMSCKESDRAMVD[7:0]LCD4LCDVD[3:0]VD[7:4]VFRAMELCDVMVMLCDVLINEVLINELCDLCDVCLKLCDVCLKLCDTOUT[4:0]TCLKEINT[7:0]nXDREQ[1:0]DMAnXDACK[1:0]DMARxD[1:0]UARTTxD[1:0]UARTnCTS[1:0]UARTnRTS[1:0]UARTIICSDAIICIICSCLIICIISLRCKIISIISDOIISIISDIIISIISCLKIISCODECLKCODECSIORXDSIOSIOTXDSIOSIOCKSIOSIORDYSIODMASIOAIN[7:0]ADCAREFTADCAREFBADCAVCOMADCP[70:0]I/OnRESETnRESETS3C44B0XnRESET4MCLKOM[3:2]OM[3:2]00=Crystal(XTAL0,EXTAL0),PLLon01=EXTCLK,PLLon10,11=Chiptestmode.EXTCLKOM[3:2]3.3V.XTAL03.3V.EXTAL0XTAL0PLLCAP700PFXTAL1RTCEXTAL1RTCXTAL1CLKoutnTRSTTAPnTRSTTAPTAPdebugger10KnTRSTTMSTAPTAP10KTCKTAPJTAG10KTDITAP10KTDOTAPVDDS3C44B0X2.5VVSS:S3C44B0X.VDDIO:S3C44B0XI/O(3.3V).VSSIO:S3C44B0XI/O.RTCVDD:RTC(2.5V3V,3.3V).VDDADC:ADC(2.5V).VSSADC:ADC.341BWSCON0x01C80000R/W0BITST731BANK7SR