三星的S3C44B0X中文数据手册

1产品预览介绍三星的S3C44B0X16/32位RISC处理器被设计来为手持设备等提供一个低成本高性能的方案。S3C44B0X提供以下配置：2.5VARM7TDMI内核带有8Kcache;可选的internalSRAM;LCDController(最大支持256色STN，使用LCD专用DMA)；2-chUARTwithhandshake(IrDA1.0,16-byteFIFO)/1-chSIO；2-chgeneralDMAs/2-chperipheralDMAswithexternalrequestpins；Externalmemorycontroller(chipselectlogic,FP/EDO/SDRAMcontroller)；5-chPWMtimers&1-chinternaltimer；WatchDogTimer；71generalpurposeI/Oports/8-chexternalinterruptsource；RTCwithcalendarfunction；8-ch10-bitADC；1-chmulti-masterIIC-BUScontroller；1-chIIS-BUScontroller；Sync.SIOinterfaceandOn-chipclockgeneratorwithPLL.。S3C44B0X采用一种新的三星ARMCPU嵌入总线结构-SAMBA2，最大达66MHZ。电源管理支持：Normal,Slow,Idle,andStopmode。系统管理功能：1Little/Bigendiansupport.2Addressspace:32Mbytespereachbank.(Total256Mbyte)3Supportsprogrammable8/16/32-bitdatabuswidthforeachbank.4Fixedbankstartaddressandprogrammablebanksizefor7banks.5.8memorybanks.-6memorybanksforROM,SRAMetc.-2memorybanksforROM/SRAM/DRAM(FastPage,EDO,andSynchronousDRAM)FullyProgrammableaccesscyclesforallmemorybanks.Supportsexternalwaitsignaltoexpendthebuscycle.Supportsself-refreshmodeinDRAM/SDRAMforpower-down.Supportsasymmetric/symmetricaddressofDRAM.Cache和内部存储器功能:4-waysetassociativeID(Unified)-cachewith8Kbyte.The0/4/8KbytesinternalSRAMusingunusedcachememory.PseudoLRU(LeastRecentlyUsed)ReplaceAlgorithm.Writethroughpolicytomaintainthecoherencebetweenmainmemoryandcachecontent.Writebufferwithfourdepth.Requestdatafirstfilltechniquewhencachemissoccurs.时钟和电源管理LowpowerTheon-chipPLLmakestheclockforoperatingMCUatmaximum66MHz.Clockcanbefedselectivelytoeachfunctionblockbysoftware.Powermode:Normal,Slow,IdleandStopmode.Normalmode:Normaloperatingmode.Slowmode:LowfrequencyclockwithoutPLLIdlemode:StoptheclockforonlyCPUStopmode:AllclocksarestoppedWakeupbyEINT[7:0]orRTCalarminterruptfromidlemode.中断控制器30Interruptsources(Watch-dogtimer,6Timer,6UART,8Externalinterrupts,4DMA,2RTC,1ADC,1IIC,1SIO)VectoredIRQinterruptmodetoreduceinterruptlatency.Level/edgemodeontheexternalinterruptsourcesProgrammablepolarityofedgeandlevelSupportsFIQ(FastInterruptrequest)forveryurgentinterruptrequest定时器功能5-ch16-bitTimerwithPWM/1-ch16-bitinternaltimerwithDMA-basedorinterrupt-basedoperationProgrammabledutycycle,frequency,andpolarityDead-zonegeneration.Supportsexternalclocksource.RTC功能:Fullclockfeature:msec,sec,min,hour,day,week,month,year.32.768KHzoperation.AlarminterruptforCPUwake-up.Timetickinterrupt通用输入输出口功能:8externalinterruptports71multiplexedinput/outputportsUART功能:2-channelUARTwithDMA-basedorinterrupt-basedoperationSupports5-bit,6-bit,7-bit,or8-bitserialdatatransmit/receiveSupportsH/Whandshakingduringtransmit/receiveProgrammablebaudrateSupportsIrDA1.0(115.2kbps)LoopbackmodefortestingEachchannelhavetwointernal32-byteFIFOforRxandTx.DMA控制器功能:2channelgeneralpurposeDirectMemoryAccesscontrollerwithoutCPUintervention.2channelBridgeDMA(peripheralDMA)controller.SupportIOtomemory,memorytoIO,IOtoIOwiththeBridgeDMAwhichhas6type'sDMArequestor:Software,4internalfunctionblocks(UART,SIO,Timer,IIS),andExternalpins.ProgrammablepriorityorderbetweenDMAs(fixedorround-robinmode)BursttransfermodetoenhancethetransferrateontheFPDRAM,EDODRAMandSDRAM.Supportsfly-bymodeonthememorytoexternaldeviceandexternaldevicetomemorytransfermodeA/D转换器:8-chmultiplexedADC.Max.100KSPS/10-bit.LCD控制器:Supportscolor/monochrome/grayLCDpanelSupportssinglescananddualscandisplaysSupportsvirtualscreenfunctionSystemmemoryisusedasdisplaymemoryDedicatedDMAforfetchingimagedatafromsystemmemoryProgrammablescreensizeGraylevel:16graylevels256Colorlevels看门狗定时器:16-bitWatchdogTimerInterruptrequestorsystemresetattime-outIIC-BUS接口1-chMulti-MasterIIC-Buswithinterrupt-basedoperation.Serial,8-bitoriented,bi-directionaldatatransferscanbemadeatupto100Kbit/sinthestandardmodeorupto400Kbit/sinthefastmode.IIS-BUS接口1-chIIS-busforaudiointerfacewithDMA-basedoperation.Serial,8/16bitperchanneldatatransfersSupportsMSB-justifieddataformatSIO(同步串口):1-chSIOwithDMA-basedorinterrupt–basedoperation.Programmablebaudrates.Supportsserialdatatransmit/receiveoperations8-bitinSIO.操作电压范围:核电压:2.5VI/O电压:3.0Vto3.6V工作频率:Upto66MHz封装:160LQFP/160FBGA2管脚描述om[1:0]:输入om[1:0]设置S3C44B0X在测试模式和确定nGCS0的总线宽度,逻辑电平在复位期间由这些管脚的上拉下拉电阻确定.00:8-bit01:16-bit10:32-bit11:TestmodeADDR[24:0]输出:地址总线输出相应段的存储器地址.DATA[31:0]输入输出:数据总线,总线宽度可编程为8/16/32位nGCS[7:0]输出:芯片选择,当存储器地址在相应段的地址区域时被激活.存取周期和段尺寸可编程.nWE输出:写允许信号,指示当前的总线周期为写周期.nWBE[3:0]输出:写字节允许信号nBE[3:0]输出:在使用SRAM情况下字节允许信号.nOE输出:读允许信号,指示当前的总线周期为读周期.nXBREQ输入:nXBREQ总线控制请求信号，允许另一个总线控制器请求控制本地总线，nXBACK信号激活指示已经得到总线控制权。nXBACK输出：总线应答信号。nWAIT输入：nWAIT请求延长当前的总线周期，只要nWAIT为低，当前的总线周期不能完成。ENDIAN输入：它确定数据类型是littleendian还是bigendian，逻辑电平在复位期间由该管脚的上拉下拉电阻确定.0:littleendian1:bigendiannRAS[1:0]输出：行地址选通信号。nCAS[3:0]输出：列地址选通信号。nSRAS输出：SDRAM行地址选通信号。nSCAS输出：SDRAM列地址选通信号。nSCS[1:0]输出：SDRAM芯片选择信号。DQM[3:0]输出：SDRAM数据屏蔽信号。SCLK输出：SDRAM时钟信号。SCKE输出：SDRAM时钟允许信号。VD[7:0]输出：LCD数据线，在驱动4位双扫描的LCD时，VD[3:0]为上部显示区数据，VD[7:4]为下部显示区数据。VFRAME输出：LCD场信号，指示一帧的开始，在开始的第一行有效。VM输出：VM极性变换信