DDR PHY Interface Specification v3_0

DDRPHYInterface,Version3.01of133May18,2012Copyright1995-2012,CadenceDesignSystems,Inc.DFIDDRPHYInterfaceDFI3.0Specification18May20122of133DDRPHYInterface,Version3.0Copyright1995-2012,May18,2012CadenceDesignSystems,Inc.ReleaseInformationRev#DateChange1.030Jan2007InitialRelease2.017Jul2007Modifications/AdditionsforDDR3Support2.021Nov2007Additionalmodifications/additionsforDDR3support.Addedreadandwriteleveling.ChangesapprovedbytheTechnicalCommitteeforDDR3support.2.021Dec2007RemovedreferencestodataeyetrainingforPHYEvaluationmode,addedagatetraining-specificmodesignal,correctedreferencesandclarifiedreadtraining.2.011Jan2008Modifiedwording;standardizednotationsinfigures,clarifiedterminologyforreadandwriteleveling.2.026Mar2008Addedtimingparametertrdlvl_enandtwrlvl_en,signaldfi_rdlvl_edge2.12Oct2008AddedinitialLPDDR2supportandcorrectedminorerrorsfrom2.0release2.124Nov2008Addedfrequencychangeprotocol,signaltimingdefinitions,trdlvl_loadandtwrlvl_loadtimingparametersandadjusteddiagramsaccordingly2.130Jan2009AddedDFIlogo2.131Mar2009Updatedwidthofdfi_rdlvl_edge,correctederroneousfigures,updatedtrdlvl_enandtwrlvl_endefinitions2.120May2009Addedlowpowercontrolinterface,modifiedlevelingrequestsignaldescriptiontoincludefrequencychange,addeddfi_data_byte_disablesignalandtphy_wrdatatimingparameters.AddedDIMMsupporttothestatusinterfaceandupdatedfrequencyratiosfromanexampletoadefinedmethod.Updatedfrequencyratiosinformationfornewproposals,modifieddefaultvaluesandrequirementsforsometraininginterfacesignals,incorporatedLPDDR2trainingoperationschanges2.122Jun2009Expandedfrequencyratioinformationtoincludevectoredreaddata,expandeduseofdfi_init_start,addedtimingdiagramsfor1:4frequencyratiosystems2.1.123Mar2010AddedreferencetotheparityinterfacetotheOverview.Changeddfi_parity_insignaltohaveaphaseindex.Modifieddescriptionofdfi_freq_ratiosignaltomakeitoptionalexceptforMCs/PHYsthatsupportmultiplefrequencyratios.Expandedfigure32intotwofigurestorepresentoddandeventimingparameters.2.1.101Apr2010Changedminimumvaluefortlp_wakeup2.1.120Apr2010Correctedfigure3timingviolation.Correctederroneoussentencefor2Ttiming.Correctedfigure35tphy_wrlattiming.Correctincorrectreferencestotphy_wrlatinfrequencyratioreadexamples.DDRPHYInterface,Version3.03of133May18,2012Copyright1995-2012,CadenceDesignSystems,Inc.2.1.127May2010AddedFigure4andtexttoexplaindifferencesbetweenFigure3and4.2.1.109Jun2010Modifiedtextindfi_init_startandsurroundingfigures3and4formoreclarity.3.021May2012AddedDDR4DRAMsupportfor:CRC,CAparitytiming,CRCandCAparityerrors,DBI,levelingsupport,andCAmodifications.AddedDFIreaddatarotationclarification,readdatapointerresynchronization,independenttimingofDFIreaddatavalidperdataslice,datapathchipselect,errorinterface,andprogrammableparameters.RenamedPHYevaluationmode.RemovedMCevaluationmodeandtphy_wrdelaytimingparameter.Addedsupportforrefreshduringtraining,multipleCStraining,enhancementstotheupdateinterfaceandtheidlebusdefinition.ProprietaryNoticeNopartofthisdocumentmaybecopiedorreproducedinanyformorbyanymeanswithoutpriorwrittenconsentofCadence.Cadencemakesnowarrantieswithrespecttothisdocumentationanddisclaimsanyimpliedwarrantiesofmerchantabilityorfitnessforaparticularpurpose.Informationinthisdocumentissubjecttochangewithoutnotice.Cadenceassumesnoresponsibilityforanyerrorsthatmayappearinthisdocument.Exceptasmaybeexplicitlysetforthinsuchagreement,Cadencedoesnotmake,andexpresslydisclaims,anyrepresentationsorwarrantiesastothecompleteness,accuracy,orusefulnessoftheinformationcontainedinthisdocument.Cadencedoesnotwarrantthatuseofsuchinformationwillnotinfringeanythirdpartyrights,nordoesCadenceassumeanyliabilityfordamagesorcostsofanykindthatmayresultfromuseofsuchinformation.©2012CadenceDesignSystems,Inc.Allrightsreservedworldwide.Portionsofthismaterialare©JEDECSolidStateTechnologyAssociation.Allrightsreserved.Reprintedwithpermission.RESTRICTEDRIGHTSLEGENDUse,duplication,ordisclosurebytheGovernmentissubjecttorestrictionsassetforthinsubparagraphs(c)(1)(ii)oftheRightsinTechnicalDataandComputerSoftwareclauseatDFARS252.227-7013.DestinationControlStatementAlltechnicaldatacontainedinthisproductissubjecttotheexportcontrollawsoftheUnitedStatesofAmerica.DisclosuretonationalsofothercountriescontrarytoUnitedStateslawisprohibited.Itisthereader'sresponsibilitytodeterminetheapplicableregulationsandtocomplywiththem.TrademarksCadenceandtheCadencelogoareregisteredtrademarksofCadenceDesignSystems,Inc.Allotherproductsorbrandnamesmentionedaretrademarksorregisteredtrademarksoftheirrespectiveholders.EndUserLicenseAgreement21.SubjecttotheprovisionsofClauses2,3,4,5and6,Cadenceherebygrantstolicensee(Licensee)aperpetual,nonexclusive,nontransferable,royaltyfree,worldwidecopyrightlicensetouseandcopytheDFI(DDRPHYInterface)specification(theDFISpecification)forthepurposeofdeveloping,havingdeveloped,manufacturing,havingmanufactured,offeringtosell,selling,supplyingorotherwisedistributingproductswhichcomplywiththeDFISpecification.4of133DDRPHYInterface,Version3.0Copyright1995-2012,May18,2012Cadenc