基于FPGA的CAN控制器软核的设计与实现

合肥工业大学硕士学位论文基于FPGA的CAN控制器软核的设计与实现姓名：潘玉静申请学位级别：硕士专业：信号与信息处理指导教师：吴从中2011-04基于FPGA的CAN控制器软核的设计与实现摘要现场总线技术是目前自动控制领域昀热门的技术之一。CAN（ControllerAreaNetwork）总线是重要的现场总线之一，遵从OSI模型，主要工作在物理层和数据链路层。CAN总线是一种全数字，多主机的异步串行总线，有着高效的报文过滤机制，错误检测机制，高速的远距离传输，以及便利的应用层接口等良好性能。目前CAN总线已在汽车工业、航空工业、工业控制等领域中得到广泛的应用，并正向更多的领域发展。目前市面上存在的都是标准定制的CAN控制器芯片，因此CAN总线设计的关键也就在于如何设计和使用它们。然而这些CAN控制器芯片接口固定，通用性差，不能兼容，且不易集成到已有的嵌入式系统中，若要实现额外功能还需外接电路。可将CAN控制器设计成软核，通过在单片FPGA中构建CAN总线系统来解决上述不足，同时还可在FPGA的剩余资源上集成其他自行设计的数字电路，可有效减少外围芯片的数量。本论文的重点是CAN控制器的前端设计，即用VerilogHDL语言完成CAN协议的物理层和数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Spartan3E上通过仿真验证，证明其正确性。论文首先分析CAN2.0协议，并通过对现有的CAN控制器芯片的分析，确定本文的CAN控制器结构，将其分解为即相互独立又相互关联的功能模块，包括接口逻辑、寄存器模块和核心模块。再进一步阐述各功能模块的设计思想和设计流程。接口管理逻辑提供WISHBONESOC与单片机两种可选的接口方式，满足各种设备的CAN总线接口设计方案。寄存器模块参照SJA1000进行设计。核心模块包括两部分：一是位流处理器，主要包括接收部分、发送部分、位填充、CRC校验、验收滤波、错误管理逻辑等；二是位时序逻辑，主要包括位定时和同步。设计每一模块之后，都通过了时钟周期为10ns的条件下的仿真验证，达到了设计要求，为未来将更多的定制功能同CAN总线控制器功能结合，融入一块FPGA芯片打下基础。关键词：CAN总线；CAN2.0协议；CAN控制器软核；VerilogHDL；FPGADesignandimplementationofaCANControllerSoftCorebasedonFPGAABSTRACTThetechnologyoffieldbusisoneofthehottesttechnologiesintheautomaticcontrolfield.CANbus(ControllerAreaNetwork)isoneofthemostimportantfieldbus,whichmainlyworkindatalinklayerandphysicallayer.It'sfullyaccordancetotheOSIsystem.CANbusisafullydigital,multimasterandasynchronousserialsfieldbus.Ithasthefeatureofmessagefilter,errormanagementsystem,highspeedandlongdistantcommunication,andtheeasyinterfacetotheapplicationlayer.Nowadays,CANbusiswidelyusedinautoindustry,aviationindustry,automaticcontrol,andtheapplicationinotherfieldisrapidlydeveloped.Nowchipsavailableinthemarketarecustomizedwithallkindsofstandards,sothekeytodesignCANbusishowtodesignandusethem.However,theseCANcontrollerchipshavefixedinterfaces,pooruniversaluse,cannotbecompatibleandeasilyintegratedintoexistingembeddedsystems.Ifwehopetoimplementadditionalfeatures,weneedtobuildexternalcircuitry.Toaddressaboveshortcomings,wecandesignaCANcontrollersoftcore,andbuildCANbussysteminasingleFPGA.Meanwhile,wecanintegrateotherdigitalcircuitintheremainingresourcesoftheFPGAtoreducethenumberofperipheralchips.Themainpurposeistocompletethefront-enddesignofCANcontrollerusingFPGA．ThatmeanstocompletetheRTL-IeveldesignofDataLinklayerandPhysicallayerinCANprotocolbyusingVerilogHDL,andtoachieveitsfunction,thentoevaluatethedesignthroughthesimulationontheplatformSpartan3E.Firstly,weanalyzeCAN2.0Protocol．Secondly,afteranalysisingtheexistingCANcontrollerchipswedeterminetheCANcontrollerstructureofthispaper,andsplittheentireCANcontrollerintoseveralmoduleswhichareindependentbutassociatedwitheachother,includingInterfaceManagementLogic(IML),RegistersandCAN_Core．Theirfunctionandprincipleareintroducedtoo．IMLprovidestwooptionalinterfacemode,includingWISHBONESOCandSCM,whichmeetdiverseinterfacedesignofequipmenttoCANbus.Registers’designrefersSJA1000.CAN_Coreconsistsoftwoparts:BitStreamProcessor(BSP),includingreceivingpart,sendingpart,bitstuffing,CRCchecking,acceptancefiltering,errormanagementlogic;thesecondisBitTimingLogic(BTL),includingbittimingandsynchronization.Insimulating,wesupposetheclockcycletobe10ns，andunderthiscondition,themodulesarefoundtomeetthedesignrequirements．Inotherwords，wehavelaidthefoundationforincorporatingmorefunctionsintoCANcontrollerbasedonFPGA．Keywords:CANbus；CAN2.0protocol；CANcontrollersoftcore；VerilogHDL；FPGA插图清单图1.1有CAN和无CAN的汽车电子系统对比...........................................2图1.2CAN节点的实现方式...................................................................................2图1.3硬IP和软IP的复用过程................................................................................5图2.1FPGA设计流程...............................................................................................8图3.1CAN的分层结构.........................................................................................10图3.2数据帧的组成...............................................................................................11图3.3标准格式和扩展格式的数据帧结构........................................................11图3.4CRC场结构...................................................................................................12图3.5应答场结构...................................................................................................13图3.6远程帧结构...................................................................................................13图3.7错误帧结构...................................................................................................13图3.8超载帧结构...................................................................................................14图3.9“错误激活”的帧间空间结构................................................................14图3.10“错误认可”的帧间空间结构.................................................................14图3.11正常位时间的组成.....................................................................................17图4.1SJA1000的功能框图...................................................................................19图4.2CAN控制器功能框图.................................................................................20图4.3CAN_Co