基于FPGA的RFID阅读器设计_张捍东

PROCESSAUTOMATIONINSTRUMENTATIONVol130No15May2009(:50407017);(:2006KJ019A2007KJ052A):2008-06-25,,1963,2003,,;FPGARFIDDesignofRFIDReaderBasedonFPGA(,243002):,RFID,,FPGA,CRC,:FPGA:TN91112:AAbstract:Asatechniquehavingwidespreadapplicableprospect,theRFIDreaderhaselaboratedgreateffectsinmanyfields.Sincedevelopingsinglechipcomputertakeslongperiod,andproducinginsmalllots,thehighfrequencyandlongdistancereaderisdesignedbyadoptingFPGAasthekernel.ItisverifiedthatthereaderisabletodecodeManchestercodeandrealizeCRCcheck.Anuniversalasynchronoustransceiverisalsodesignedtoimplementsendingdataandreceivingdata.Thedesignfeaturessimplecircuitry,andeasytotransplant.Keywords:RFIDReaderFPGADecodeUniversalasynchronoustransceiver0RFID(radiofrequencyidentification),,,RFID,FPGAPLD(programmablelogicdevice),ASIC,ASIC,,FPGARFID1ISO/IEC1800026ISO/IEC18000,(860960MHz)[1],TypeATypeB,11Tab.1Comparisonof2typesofradiofrequencymodulesTypeATypeBCRC216CRC21664bits64bits256bits/8bits/TypeB,915MHz,11Fig.1ResponseformatofthetagFPGAJTAG(RS2232),22Fig.2StructuraldiagramofthereaderFPGAEP1C6Q240C8SRAM,,5980,185,JTAGPC06FPGARFID,30520095RS2232,RS2232AutoShutdownMA3231,[2]:,NRZManchester,,,,Manchester;NRZUART;,CRC(cyclicredundancycheck),UARTXMIT_CMD,CRC,XMIT_CMD1,2EP1C6Q240C8,Quartus,VHDL,ModelSimQuartusAlteraPLD,VHDLVerilog2HDL,,PLDQuartus[3]2.1Manches2ter,,,,,,(/),101,010[4]915MHz,Manchester915MHz/16915MHzclk,16(clk/16)8(clk/8)2D,clk/8,Manchester,2q1q0,clk/16,Manchester,q0=1,q1=0,1;q0=0,q1=1,0ManchesterQuartus,RTL,3mdiManchester,Out13RTLFig.3RTLviewofthedecodeblock,,22Tab.2TheusedchipresourcesLogiccellsLCregistersPinsRegister2onlyLCsLUTCarrychainLCs884265ModelSim,44Fig.4Decodesimulationwaveform4:mdiManchester1010011010011001;Out111011010Manchester1561264ns,,2.2,16FPGARFID,PROCESSAUTOMATIONINSTRUMENTATIONVol130No15May2009R_START()R_CENTER()R_WAIT()R_SAMPLE()R_STOP()5,55UARTFig.5ReceivingstatusprincipleofUARTRXD_SYNC10,0,[5]balk16,01/4R_CENTER,,balk(RCNT16)R_WAIT,15balk,16balk,R_WAIT(FRA2MELEN),,R_START,CRC,,XMIT_CMD_P1,2.3CRC,CRC,CRCCRC:x16+x12+x5+116,8bits,8,,2.4X_START,0TXD[6],X_WAITXCNT16balkX_WAITR_WAIT15,X_SHIFT,,X_WAIT,X_STOP,3EP1C6Q240C8JTAG[7],JTAG10,10,6(nCE0,DA2TA0DCLK)6Fig.6Circuitdiagramofconfiguration4FPGASoC,ISO/IEC1800026,[1],,.RFID[J].,2006(3):75-78.[2],,.nRF401[J].,2005,26(7):27-29.[3],.EDAFPGA[J].,2002(1):70-73.[4],,.FPSLIC[J].,2006,43(2):36-38.[5]ZhangJianmin,XieZeming,LaiShengli,etal.AdesignofRFre2ceivingcircuitofRFIDreader[C]//The4thInternationalConfer2enceonMicrowaveandMillimeterWaveTechnologyProceedings,2004:406-409.[6]LiakotA,RoslinaS,IshakA.Designofamicro2UARTforsocapplica2tion[J].ComputersandElectricalEngineering,2004,30(4):257-268.[7],.FPGA[M].:,2005:203-208.26FPGARFID,