74hc32芯片参数

©SemiconductorComponentsIndustries,LLC,2007March,2007−Rev.11PublicationOrderNumber:74HC32/D74HC32Quad2−InputORGateHigh−PerformanceSilicon−GateCMOSThe74HC32isidenticalinpinouttotheLS32.ThedeviceinputsarecompatiblewithStandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLSTTLoutputs.Features•OutputDriveCapability:10LSTTLLoads•OutputsDirectlyInterfacetoCMOS,NMOSandTTL•OperatingVoltageRange:2.0to6.0V•LowInputCurrent:1.0A•HighNoiseImmunityCharacteristicofCMOSDevices•InComplianceWiththeJEDECStandardNo.7ARequirements•ESDPerformance:HBM2000V;MachineModel200V•ChipComplexity:48FETsor12EquivalentGates•ThesearePb−FreeDevices=DeviceCodeA=AssemblyLocationL,WL=WaferLotY=YearW,WW=WorkWeekGor=Pb−FreePackageTSSOP−14DTSUFFIXCASE948G141SOIC−14DSUFFIXCASE751A141HC32GAWLYWW114HC32ALYW114Seedetailedorderingandshippinginformationinthepackagedimensionssectiononpage2ofthisdatasheet.ORDERINGINFORMATION(Note:Microdotmaybeineitherlocation)74HC32=VCCPIN7=GNDLOGICDIAGRAM2B16Y24A25B28Y39A310B311Y412A413B4Y=A+BPinout:14−LeadPackages(TopView)1314121110982134567VCCB4A4Y4B3A3Y3A1B1Y1A2B2Y2GNDLLHHLHLHFUNCTIONTABLEInputsOutputABLHHHYORDERINGINFORMATIONDevicePackageShipping†74HC32DR2GSOIC−14(Pb−Free)2500/Tape&Reel74HC32DTR2GTSSOP−14*†Forinformationontapeandreelspecifications,includingpartorientationandtapesizes,pleaserefertoourTapeandReelPackagingSpecificationsBrochure,BRD8011/D.*ThispackageisinherentlyPb−Free.74HC32(ReferencedtoGND)–0.5to+7.0VVinDCInputVoltage(ReferencedtoGND)–0.5toVCC+0.5VVoutDCOutputVoltage(ReferencedtoGND)–0.5toVCC+0.5VIinDCInputCurrent,perPin±20mAIoutDCOutputCurrent,perPin±25mAICCDCSupplyCurrent,VCCandGNDPins±50mAPDPowerDissipationinStillAir,SOICPackage†TSSOPPackage†500450mWTstgStorageTemperature–65to+150CTLLeadTemperature,1mmfromCasefor10SecondsSOICorTSSOPPackage260CStressesexceedingMaximumRatingsmaydamagethedevice.MaximumRatingsarestressratingsonly.FunctionaloperationabovetheRecommendedOperatingConditionsisnotimplied.ExtendedexposuretostressesabovetheRecommendedOperatingConditionsmayaffectdevicereliability.†Derating—SOICPackage:–7mW/Cfrom65to125CTSSOPPackage:−6.1mW/Cfrom65to125CForhighfrequencyorheavyloadconsiderations,seeChapter2oftheONSemiconductorHigh−SpeedCMOSDataBook(DL129/D).RECOMMENDEDOPERATINGCONDITIONSSymbolParameterMinMaxUnitVCCDCSupplyVoltage(ReferencedtoGND)2.06.0VVin,VoutDCInputVoltage,OutputVoltage(ReferencedtoGND)0VCCVTAOperatingTemperature,AllPackageTypes–55+125Ctr,tfInputRiseandFallTimeVCC=2.0V(Figure1)VCC=4.5VVCC=6.0V0001000500400nsThisdevicecontainsprotectioncircuitrytoguardagainstdamageduetohighstaticvoltagesorelectricfields.However,precautionsmustbetakentoavoidapplicationsofanyvoltagehigherthanmaximumratedvoltagestothishigh−impedancecir-cuit.Forproperoperation,VinandVoutshouldbeconstrainedtotherangeGND(VinorVout)VCC.Unusedinputsmustalwaysbetiedtoanappropriatelogicvoltagelevel(e.g.,eitherGNDorVCC).Unusedoutputsmustbeleftopen.74HC32(VoltagesReferencedtoGND)VCC(V)GuaranteedLimitSymbolParameterCondition−55to25°C≤85°C≤125°CUnitVIHMinimumHigh−LevelInputVoltageVout=0.1VorVCC−0.1V|Iout|≤20A2.03.04.56.01.502.103.154.201.502.103.154.201.502.103.154.20VVILMaximumLow−LevelInputVoltageVout=0.1VorVCC−0.1V|Iout|≤20A2.03.04.56.00.500.901.351.800.500.901.351.800.500.901.351.80VVOHMinimumHigh−LevelOutputVoltageVin=VIHorVIL|Iout|≤20A2.04.56.01.94.45.91.94.45.91.94.45.9VVin=VIHorVIL|Iout|≤2.4mA|Iout|≤4.0mA|Iout|≤5.2mA3.04.56.02.483.985.482.343.845.342.203.705.20VOLMaximumLow−LevelOutputVoltageVin=VIHorVIL|Iout|≤20A2.04.56.00.10.10.10.10.10.10.10.10.1VVin=VIHorVIL|Iout|≤2.4mA|Iout|≤4.0mA|Iout|≤5.2mA3.04.56.00.260.260.260.330.330.330.400.400.40IinMaximumInputLeakageCurrentVin=VCCorGND6.0±0.1±1.0±1.0AICCMaximumQuiescentSupplyCurrent(perPackage)Vin=VCCorGNDIout=0A6.02.02040ANOTE:InformationontypicalparametricvaluescanbefoundinChapter2oftheONSemiconductorHigh−SpeedCMOSDataBook(DL129/D).ACCHARACTERISTICS(CL=50pF,Inputtr=tf=6ns)VCC(V)GuaranteedLimitSymbolParameter−55to25°C≤85°C≤125°CUnittPLH,tPHLMaximumPropagationDelay,InputAorBtoOutputY(Figures1and2)2.03.04.56.07530151395401916110552219nstTLH,tTHLMaximumOutputTransitionTime,AnyOutput(Figures1and2)2.03.04.56.07527151395321916110362219nsCinMaximumInputCapacitance101010pFNOTE:Forpropagationdelayswithloadsotherthan50pF,andinformationontypicalparametricvalues,seeChapter2oftheONSemiconductorHigh−SpeedCMOSDataBook(DL129/D).CPDPowerDissipationCapacitance(PerBuffer)*Typical@25°C,VCC=5.0V,VEE=0VpF20*Usedtodeterminetheno−loaddynamicpowerconsumption:PD=CPDVCC2f+ICCVCC.Forloadconsiderations,seeChapter2oftheONSemiconductorHigh−SpeedCMOSDataBook(DL129/D).74HC32**IncludesallprobeandjigcapacitanceTESTPOINT90%50%10%tTLHDEVICEUNDERTESTOUTPUTFigure2.TestCircuitYABFigure3.ExpandedLogicDiag