New_High_Speed_PCB_Board_Design

HighSpeedPCBDesignHighSpeedPCBDesignRidetheWaveWorkshopPostRouteAnalysisofaHighPostRouteAnalysisofaHighSpeedPCBDesignSpeedPCBDesignDesign/AnalysisforPowerDeliverySystem(PDS)PostRouteAnalysisofaHighPostRouteAnalysisofaHighSpeedPCBDesignSpeedPCBDesign•Intoday’sworld,thedemandforultra-high-speedPCBdesignisontherise•Engineersareassignedthetaskofdesignmixedanalogandfastrise-timedigitalboards,andhaveallsignalsarriveattheirdestinationcleanly•Withtheadvanceofhighlyspecializeddesignandlayoutsoftware,thedesignoftheseboardshasbecomeincreasingly‘easy’(automated)•Thesephysicaldesignandlayouttoolscanbeprovidedwithdesignconstraintsandauto-routedeasily,resultinginincreasedproductivityofthelayoutengineerandcontributionstosignalintegrityproblemsDesigningfortheFuture•TheadvancementofdesignandlayoutsoftwareneedstobematchedbytheaccompanyingadvancementinpowerfulANALYSIStoolsusedtosolvetimingdelays,mismatchedlineimpedances,crosstalk,anddielectriclossonhighspeedlines•Justasanauto-layoutprogramcannotlayout100percentofthenetsonacomplex,high-speedboard,ananalysistoolcannotdefaultto2-dimensionalfieldsolversandbehavioralmodelson100percentofthenetsonaPCB.•Manynetsonaboardmaybeanalyzedaccuratelyusing2-dsolvers.However,criticalsignalswillrequireafull3-dsolverthatdoesnotdefaulttoan‘ideal’caseforthecurrentreturnpath.Thefull3-dsolverwilltakeintoaccountgroundplaneswithholes,cutoutsorthataresplit.Changesinreferenceplanes,cutouts,andcouplingtopower/groundplanesareothersituationsthatrequireafull3-dsolverDesigningfortheFuture•ShowtheintegrationbetweenAllegroandPCB/MCM•Showmixed2Dand3Dextractions•Showsinglenetandmultiplenetsimulations•Showhowtoinvestigatesignalintegrityissuescausedbymeanderingtracesusedfortimingdelays•ShowCrosstalksimulationsonavictimnetinthedesign•Showhowtosetupupdifferentialpairsimulations•Showcomparisonbetweenfull3DPEECsolutionsandmixed2D/3DsubcircuitsGoalsforthisPresentationINTEGRATIONAutomaticTranslationNetNameMAA42DCross-sectionofeverynetinboard3DViaparasiticscalculatedforeveryviainboard3DViaParasiticsA3Dmodelisusedtocalculateallviaparasitics.SingleNet-by-NetSimulationsRisetimeof500ps.NearEndFarEndSourceSingleNet-by-NetSignalIntegrityViolations•QuicklyscreeninformationforeverynetontheboardforviolationssuchasPropagationDelayandSettlingtimesRisetimeof200ps.NearEndFarEndSourceSingleNet-by-NetSimulationsSingleNet-by-NetSimulationsRisetimeof200ps.withcouplingSourceNearEndFarEndCoupledtracesCrosstalkSimulation–TheSetupBVictimNet–MAB9AggressorNets–MAA4,MAA5AggressorNets–MAA9,MAB10!Create2Dcross-sectionsofsinglelineandmutualparasiticsforall5nets!Apply3.3VpulsetooneterminalofMAA4,MAA5,MAA9andMAB10,andput75ohmterminatorsontheotherterminals!TerminatenetMAB9with75ohmterminatorsateachendTheabove3stepsaredonebytheprogramautomatically.!Firstrunsimulationwith0.5nsrise/falltime,thenrunagainwith0.2nsrise/falltimeCrosstalkSimulation–TheSetupNearEndFarEndRisetimeof500ps.CrosstalkSimulationsNearEndFarEndRisetimeof200ps.CrosstalkSimulationsMD32MD33DifferentialPairDifferentialSignalingwithLinearSourceSourceNearEndFirstViaSecondViaRisetimeof200ps.VccPlaneGNDPlaneWhentoAnalyzein3D?TopViewBottomView•Split/partialPlane•ViaCoupling•ChangeinReferencePlane•GroundDiscontinuity•CorrectlyModelReturnPath•Power/groundBounce+-+-ComparisonofMixed2D/3DwithIBISDriver/ReceiverMixed2D/3DParasiticExtractionPEECParasiticExtractionIBISDriverIBISDriverIBISReceiverIBISReceiverIBISDriver/ReceiverwithMixed2D/3DmodelSourceNearEndFirstViaSecondViaIBISDriver/Receiverwith3DmodelSourceNearEndFirstViaSecondViat(seconds)VoltsIBISWaveforms3DModelWhatdidwelearn?•HowPCB/MCMistightlyintegratedwithAllegro•Howautomaticallymixed2Dand3Dextractionsareperformed•Howsinglenetandmultiplenetsimulationsareperformed•HowCrosstalksimulationsonavictimnetcanbeseen•Howdifferentialsignalingcanbeperformed•Howthe3DPEECmodelcomparedwiththemixed2D/3DsimulationsusinganIBISmodelDesign/AnalysisforPowerDeliverySystem(PDS)High-SpeedDigitalDevicePowerDeliverySystemIVIVZ=TheImpedanceseeintoPDSatthedeviceshouldkeeplowfromDCtoseveralharmonicsofclockfrequency!f|Z|Mag.ofZtargetZTheImpedanceofPDSTargetImpedanceCalculation3.3v1.8vConverter3.3vVRM4A2A2A1.8vsmallplane3.3vplane()()CurrentRippleAllowedVoltageSupplyPowerZTarget×=()()Ω=×=mAvZ452%58.1v)Target(1.8()()Ω=×=mAvZ5.822%53.3v)Target(3.3HardwareExamplePDSComponentsLinearmodelforVRM.VoltageRegulatorModule(VRM)R0:thevalueoftheresistorbetweentheVRMsensepointandtheactualloadandisusuallyonlyafewmOhmsL_out:theoutputinductanceoftheVRMR_flat:theESRofthecapacitorassociatedwiththeVRMIdealvoltagesourcehasthevalueofthepowersupplyvoltageL_slewischosensothatcurrentwillberampedupinthelinearmodelinaboutthesametimethatitisrampedupinarealVRM.LinearmodelforVRM.VoltageRegulatorModule(VRM)!V=L*di/dt!ForaVRMtorampthis20Atransientcurrenteitherupordownin15usR0=1mohmL_out=4nHR_flat=30mohmL_slew=67.5nHnHAVdtdiVslewL5.6720sec151.80.05_=⋅⋅==µSimulationforVRMSimulationforVRM(cont’d)BulkCapacitor•I=C*dv/dt•Supposethereisa20Acurrenttransient,theVRMrespondsin15us,andthePDSmustremainwithin5%ofa1.8