基于VHDL的uart设计

Uart顶层文件libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityuartisport(clk,reset:instd_logic;输入时钟及复位按钮rxd:instd_logic;串行输入端txd:outstd_logic串行输出端);enduart;architecturebehavioralofuartiscomponentreceive接收器元件例化port(clkr:instd_logic;reset:instd_logic;rxd:instd_logic;frame_end:outstd_logic;dout:outstd_logic_vector(7downto0));endcomponent;componentFifoFIFO的元件例化port(clock:INSTD_LOGIC;data:INSTD_LOGIC_VECTOR(7DOWNTO0);rdreq:INSTD_LOGIC;wrreq:INSTD_LOGIC;empty:OUTSTD_LOGIC;full:OUTSTD_LOGIC;q:outstd_logic_vector(7downto0));endcomponent;componentbaud分频器的元件例化Port(clkb,resetb:instd_logic;clk_out:outstd_logic);endcomponent;componenttransmit发射器的元件例化PORT(clkt:INSTD_LOGIC;reset:INSTD_LOGIC;lock:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(7downto0);trans:OUTSTD_LOGIC;trans_end:OUTSTD_LOGIC);endcomponent;componentflag接受器工作状态原件的例化port(rxd,clk2:instd_logic;REN:outstd_logic);endcomponent;componentcounter移位寄存器的元件例化port(REN,clk2:instd_logic;w,t:outstd_logic);endcomponent;signalframe_end,clk2,wrreq,full,empty,REN,w,t,j,k:std_logic;连接线信号的说明signaldout,data,buf,q,din:std_logic_vector(7downto0);signalrdreq,lock,trans,trans_end:std_logic;beginwrreq=frame_end;data=buf;din=q;lock=j;rdreq=k;txd=trans;receive1:receiveportmap(clk,reset,rxd,frame_end,dout);例化元件的引用baud1:baudportmap(clk,reset,clk2);Fifo1:Fifoportmap(clk2,data,rdreq,wrreq,empty,full,q);transmit1:transmitportmap(clk,reset,lock,din,trans,trans_end);flag1:flagportmap(rxd,clk2,REN);counter1:counterportmap(REN,clk2,w,t);process(frame_end,dout)锁存器接收器的frame_end下，将接受器的输出寄存到beginbuf，收到wrreq信号时，写入fifoif(frame_end='1')thenbuf=dout;endif;endprocess;process(REN)输出工作状态选择器beginREN=0，处于接受状态，令fifo的读操作rdreq及发射器的锁ifREN='1'then存lock为0j=w;REN=1，接收counter提供信号w，t分别给rdreq和lockk=t;elsek='0';j='0';endif;endprocess;endbehavioral;uart编译结果Uart功能仿真结果uart时序仿真结果Uart接收器libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityreceiveisPort(clkr:instd_logic;时钟输入reset:instd_logic;复位端rxd:instd_logic;串行输入frame_end:outstd_logic;工作状态输出dout:outstd_logic_vector(7downto0));并行输出endreceive;architecturebehavioralofreceiveisbeginpro:process(clkr,reset,rxd)variablenumber:std_logic_vector(3downto0);variablecount:std_logic_vector(3downto0);variablebuf:std_logic_vector(7downto0);beginifreset='1'thennumber:=0000;count:=0000;frame_end='1';elsifrising_edge(clkr)thenifnumber=0000then判断是否接受到起始位，在clk下连续8个时钟接受为0ifrxd='0'then0则认为接受到起始位，开始接受数据ifcount1000thencount:=count+1;elsedout=00000000;count:=0000;number:=number+1;frame_end='0';endif;endif;elsifnumber=0001andnumber=1000then接受数据位ifcount1111then每16个clk时钟接受一位数据位count:=count+1;elsecount:=0000;number:=number+1;frame_end='0';buf(7downto1):=buf(6downto0);buf(0):=rxd;endif;elsifnumber=1001then接受结束位，到此一帧数据，即十位，接受完毕ifcount1111then并开始将八位数据输出count:=count+1;elsecount:=0000;dout=buf;buf:=00000000;number:=0000;frame_end='1';endif;elsecount:=0000;number:=0000;buf:=00000000;frame_end='1';endif;endif;endprocess;endbehavioral;uart接收器功能仿真结果Uart接收器时序仿真结果Uart接收器编译结果由ｑｕａｒｔｕｓ功能提供的ＦＩＦＯQuartus下megawizard工具提供的FIFO设置一路时钟输入，wrreq和rdreq分别控制写入和读出操作提供empty，full工作状态输出Data{7~0}输入并行数据Q{7~0}输出并行数据深度和宽度为8--megafunctionwizard:%FIFO%--GENERATION:STANDARD--VERSION:WM1.0--MODULE:scfifo--============================================================--FileName:Fifo.vhd--MegafunctionName(s):--scfifo----SimulationLibraryFiles(s):--altera_mf--============================================================--************************************************************--THISISAWIZARD-GENERATEDFILE.DONOTEDITTHISFILE!----9.0Build23506/17/2009SP2SJWebEdition--************************************************************--Copyright(C)1991-2009AlteraCorporation--YouruseofAlteraCorporation'sdesigntools,logicfunctions--andothersoftwareandtools,anditsAMPPpartnerlogic--functions,andanyoutputfilesfromanyoftheforegoing--(includingdeviceprogrammingorsimulationfiles),andany--associateddocumentationorinformationareexpresslysubject--tothetermsandconditionsoftheAlteraProgramLicense--SubscriptionAgreement,AlteraMegaCoreFunctionLicense--Agreement,orotherapplicablelicenseagreement,including,--withoutlimitation,thatyouruseisforthesolepurposeof--programminglogicdevicesmanufacturedbyAlteraandsoldby--Alteraoritsauthorizeddistributors.Pleaserefertothe--applicableagreementforfurtherdetails.LIBRARYieee;USEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYFifoISPORT(clock:INSTD_LOGIC;data:INSTD_LOGIC_VECTOR(7DOWNTO0);rdreq:INSTD_LOGIC;wrreq:INSTD_LOGIC;empty:OUTSTD_LOGIC;full:OUTSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDFifo;ARCHITECTURESYNOFfifoISSIGNALsub_wire0:STD_LOGIC;SIGNALsub_wire1:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALsub_wire2:STD_LOGIC;COMPONENTscfifoGENERIC(add_ram_output_register:STRING;intended_device_family:STRING;lpm_numwords:NATURAL;lpm_showahead:STRING;lpm_type:STRING;lpm_width:NATURAL;lpm_widthu:NATURAL;overflow_checking:STRING;underflow_checking:STRING;use_eab:STRING);PORT(rdreq:INSTD_LOGIC;empty:OUTSTD_LOGIC;clock:INSTD