Verilog-HDL4-7-分频代码

四分频modulequarter_clk(reset,clk_in,clk_out);inputclk_in,reset;outputclk_out;regclk_out;reg[4:0]count;always@(posedgeclk_in)beginif(!reset)clk_out=0;elseif(count1)begincount=count+1;endelsebegincount=0;clk_out=~clk_out;endendendmodule仿真`defineclk_cycle50moduletest_quarter_clk;regclk,reset;wireclk_out;always#`clk_cycleclk=~clk;initialbeginclk=0;reset=1;#100reset=0;#100reset=1;#10000$stop;endquarter_clkquarter_clk1(reset,clk,clk_out);endmodule7分频modulediv7(rst,clk,cout1,cout2,cout);inputclk,rst;outputcout1,cout2,cout;reg[2:0]m,n;wirecout;regcout1,cout2;assigncout=cout1|cout2;always@(posedgeclk)beginif(rst)begincout1=0;m=0;endelseif(!rst)beginif(m==6)beginm=0;endelsem=m+1;if(m==2)cout1=~cout1;elseif(m==5)cout1=~cout1;endendalways@(negedgeclk)beginif(rst)begincout2=0;n=0;endelseif(!rst)beginif(n==6)beginn=0;endelsen=n+1;if(n==2)cout2=~cout2;elseif(n==5)cout2=~cout2;endendEndmodule仿真`timescale1ns/1ps`defineclk_cycle50moduleqii;regclk,rst;wirecout1,cout2,cout;always#`clk_cycleclk=~clk;initialbeginclk=0;rst=1;#200rst=0;#10000$stop;enddiv7div71(rst,clk,cout1,cout2,cout);endmodule