Cadence-SystemSI-SLA.ppt

SystemSI–SerialLinkAnalysisSystemSISerialLinkAnalysis-AnalysisofMulti-GigabitSerialLinkInterfacesAgendaTrendsandchallengesIBISAMIdillikiltiIBIS-AMIandseriallinksimulationKeyFeaturesofSystemSI–SerialLinkAnalysisKeyFeaturesofSystemSI–SerialLinkAnalysisDemonstration2©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.TddChllfSilLikTrendsandChallengesforSerialLinks3©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.WhatisaSerialLink?SerializerDe-serializerParallelDataSerialDataParallelItfhllltdtidtthDataData•Interfacewhereparallelstreamsdataaremixedtogether(serialized)togetherforhigh-speeddatatransmission•Usesserializers/de-serializers,or“SerDes”components4©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.Usesserializers/deserializers,orSerDescomponentsComponentsofaSerialLinkTXTXRXRXChannel/SystemChannel/SystemTXTXRXRXInterconnectInterconnectReceiverReceiverTittTittEqualizerEqualizerClockClockRecoveryRecoveryDataDataRecoveryRecoveryTransmitterTransmitterEqualizerEqualizerSerializerSerializerFIRFIRStripline/Stripline/MicrostripMicrostripPCB/PKGPCB/PKGyyDFEDFEODTODTPrePre--emphasisemphasisFFEFFEMicrostripMicrostripConnectorsConnectorsCapacitorsCapacitorsViasViasCablesCablesBackplanesBackplanes5©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.SerialLinkInterfaces6©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.AdvantagesofSerialLinks•EliminateskewuncertaintybyremovalofmultiplesignalwiresSf•Simplifylayoutandenableincreaseddensity•Lowerpower,EMIandSSOwithfewerpinsanddifferentialsignaling•Reductionofnumberofvias•EliminatetimingconcernsthroughClockRecovery•Increasedthroughput7©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.ChallengesWithSerialLinks•Escalatingdatarates•Passiveinterconnectmodeling•ModelingSerDesequalization•Simulationcapacity8©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.EscalatingDataRates•Asdatarateincreases,thenormalizedjitterandnoiseinagivenchannelwillalsoincreasewillalsoincrease•EarlyPCIExpressranat25Gbpsat2.5Gbps•10-12.5Gbpsfairlycommonnowcommonnow•Newinterfacestodayarerunningat25Gbps!gp9©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.PassiveInterconnectModeling•NeedextractionaccuracyathigherfrequenciesPldli(•Planemodeling(ex.Swisscheese)becomesimportantbecomesimportant•Viastructures(i.e.stubs)arecritical!stubs)arecritical!10©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.ModelingSerDesEqualization•Complexequalization(EQ)oftenincludedinSerDesdevicesSEQ(DFE)iyndxndn•SomeEQ(ex.DFE)isadaptive,inthatitssettingsself-modifycdrndn+settingsself-modifywhilepassingDatatrafficWyn=xn+wi*diyn-outputxn-inputdi-previous‘ith’decisionithwi-ithtapweight11©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.EqualizationExample–Pre/De-Emphasis•Transmitter’soutputisincreasedoverthenominalvaluewhenthebitistransitioningThewaveformhighfrequencyportionistransmittedistransitioning.Thewaveformhighfrequencyportionistransmittedwithmoreenergythanthelowerfrequencyportions.•“Nontransition”bitsareattenuatedrelativetotheamplitudeofthe•Non-transitionbitsareattenuatedrelativetotheamplitudeoftheprecedingtransitionbit.12©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.SimulationCapacity•Consideralaboscilloscopeseton“infinitepersistence”•Initialeyemaybeopen,butasadditionaltrafficissampled,theeyecanclosedown•Eyeeventuallystabilizesasenoughsamplesaretaken,anduniquebitcombinationsareexhausted•Timedomainsimulationissimilar;needtorunLARGEbitstreamstogeneratestableeyediagramsfromwhichreliablemeasurementscanbetaken(otherwiseoptimistic)diagrams,fromwhichreliablemeasurementscanbetaken(otherwiseoptimistic)•Practicallyspeaking,traditionalcircuitsimulatorscanrunontheorderof100sofbits•Multi-gigabitseriallinkscancommonlytake1,000,000sofbitstoconverge,withEQAdditililtiitfldfitdiid!13©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.•Additionalsimulationcapacityofseveralordersofmagnitudeisrequired!IBISAMIdSilLikSiltiIBIS-AMIandSerialLinkSimulation14©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.Motivation•TheintentofIBIS-AMIistoenableplug-and-playiltitibilitbtSDdlfsimulationcompatibilitybetweenSerDesmodelsfromdifferentsuppliers,inastandardcommercialEDAformatTxRxPackageSystemPackagetCTLEPackageInterconnectyInterconnectPackageInterconnectFFESamplerClockrecoveryoutCTLESupplier“A”Supplier“B”15©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.SupplierASupplierBIBIS-AMIModelSub-ComponentsCiitt•Circuitpart–IObufferstage–Voltageswinggg–Parasitics–SpiceortraditionalIBISformat•Algorithmicpart–On-chipEqualizationfunctionality–Equalizationfunctionality–DLL+AMIfile16©2012CadenceDesignSystems,Inc.Cadenceconfidential.Internaluseonly.APIsinIBIS-AMIModelingAMI_Init-Initializefilter-SetupDataStructuresModelinputImpulseResponseModifiedImpulseRModelinputparametersResponseAMIGetWaveAMI_GetWave-WaveformProcessing-ClockandDataRecoveryContinuo