数字设计原理与实践第四版第一二章答案

Chapter11.2(1)Aunitwhichdescribesasingledigitofbinarynotationwasrepresentedeitherby’0’or‘1’;(2)Aunitwhichdescribesthedigitalabstractionthatassociatearangeofanalogvalueswitheachlogicvalue(0or1);(3)Aunitwhichdescribesastatefalseortruewithlogicvalue0or1;1.3ASIC:ApplicationSpecificIntegratedCircuitCAD:ComputerAidedDesignCD:CompactDiscDVD:DigitalVersatileDiscCPLD:ComplexProgrammableLogicDeviceFPGA:Field-ProgrammableGate-ArrayHDL:HardwareDescriptionLanguageIC:IntegratedCircuitIP:InternetProtocolLSI:LargeScaleIntegrationMCM:Multi-chipModuleMSI:MediumScaleIntegrationNRE:NonRecurringEngineeringPBX:PrivateBranchExchangePCB:PrintedCircuitBoardPLD:ProgrammableLogicDevicePWB:PrintedWritingBoardSMT:SurfaceMountTechnologySSI:SmallScaleIntegrationVHDL:VeryHighSpeedIntegrationCircuitHardwareDescriptionLanguageVLSI:VeryLargeScaleIntegration1.5Taperecordertomp3、TV、Camera、videocameraChapter22.1(a)6B16(d)110111.0101002(e)14.D16(i)57.348(j)101011100.0011122.2(f)4ACE.F0C162.3(f)157255.57567482.4321076543218=110100010001111101011000110100012=32180378130832182.5(g)138102.6111110122.7(a)1001101(c)1010000002.11SignedmagnitudeOne’scomplementTwos’complement+25000110010001100100011001+120011110000111100001111000+82010100100101001001010010-42101010101101010111010110-6100001101111100111111010-1111110111110010000100100012.12(a)no(b)no(c)yes(d)yes2.22(1)if(X=0&&Y=0)(2)if(X=0&&Y=0&&|X|=|Y|)[X]+[Y]=X+Y=[X+Y][X]+[Y]=X+2n-|Y|=X+Y=[X+Y](3)if(X=0&&Y=0&&|X|=|Y|)(4)if(X0&&Y0)[X]+[Y]=X+2n-|Y|=2n-|X+Y|=[X+Y][X]+[Y]=2n-|X|+2n-|Y|=2n-|X+Y|=[X+Y]2.35001/010011/100101/110111/0002.36Thehalfoftheboundarieswhichisbadboundariesis2n-1