UART通讯协议规范-8003525

UARTIPCoreSpecificationAuthor:[e-mail].0.6August11,2002ThispagehasbeenintentionallyleftblankOpenCoresUART16550corespecifications8/11/2002………………………………………………1IOports………………………………………………2Clocks………………………………………………3Registers………………………………………………4Operation………………………………………………13Architecture………………………………………………15OpenCoresUART16550corespecifications8/11/2002(UniversalAsynchronousReceiver/Transmitter)coreprovidesserialcommunicationcapabilities,whichallowcommunicationwithmodemorotherexternaldevices,likeanothercomputerusingaserialcableandRS232protocol.ThiscoreisdesignedtobemaximallycompatiblewiththeindustrystandardNationalSemiconductors’16550Adevice.Features:•WISHBONEinterfacein32-bitor8-bitdatabusmodes(selectable)•FIFOonlyoperation•RegisterlevelandfunctionalitycompatibilitywithNS16550A(butnot16450).•DebugInterfacein32-bitdatabusmode.OpenCoresUART16550corespecifications8/11/2002’sclockinputWB_RST_I1InputAsynchronousResetWB_ADDR_I5or3InputUsedforregisterselectionWB_SEL_I4InputSelectsignalWB_DAT_I32or8InputDatainputWB_DAT_O32or8OutputDataoutputWB_WE_I1InputWriteorreadcycleselectionWB_STB_I1InputSpecifiestransfercycleWB_CYC_I1InputAbuscycleisinprogressWB_ACK_O1OutputAcknowledgeofatransfer2.2OtherinternalsignalsPortWidthDirectionDescriptionINT_O1OutputInterruptoutputBAUD_O1OutputOptionalbaudrateoutputsignal.Thesignalhereisthe16xactualbaudrate.ItisenabledifUART_HAS_BAUDRATE_OUTPUTisdefined2.3External(off-chip)connectionsPortWidthDirectionDescriptionSTX_PAD_O1OutputTheserialoutputsignalSRX_PAD_I1InputTheserialinputsignalRTS_PAD_O1OutputRequestToSendDTR_PAD_O1OutputDataTerminalReadyCTS_PAD_I1InputClearToSendDSR_PAD_I1InputDataSetReadyRI_PAD_I1InputRingIndicatorDCD_PAD_I1InputDataCarrierDetectOpenCoresUART16550corespecifications8/11/2002(MHz)NameSourceMaxMinResolutionDescriptionclkWISHBONEbus1258Mhzfor1200bps3.6864for115200bpsWISHBONEclockOpenCoresUART16550corespecifications8/11/2002(THR)08WTransmitFIFOinputInterruptEnable18RWEnable/MaskinterruptsgeneratedbytheUARTInterruptIdentification28RGetinterruptinformationFIFOControl28WControlFIFOoptionsLineControlRegister38RWControlconnectionModemControl48WControlsmodemLineStatus58RStatusinformationModemStatus68RModemStatusInaddition,thereare2ClockDivisorregistersthattogetherformone16-bit.Theregisterscanbeaccessedwhenthe7th(DLAB)bitoftheLineControlRegisterissetto‘1’.Atthistimetheaboveregistersataddresses0-1can’tbeaccessed.NameAddressWidthAccessDescriptionDivisorLatchByte1(LSB)08RWTheLSBofthedivisorlatchDivisorLatchByte218RWTheMSBofthedivisorlatchWhenusing32-bitdatabusinterface,additionalread-onlyregistersareavailablefordebugpurposes:NameAddressWidthAccessDescriptionDebug1832RFirstdebugregisterDebug21232RSeconddebugregisterOpenCoresUART16550corespecifications8/11/2002(IER)ThisregisterallowsenablinganddisablinginterruptgenerationbytheUART.Bit#AccessDescription0RWReceivedDataavailableinterrupt‘0’–disabled‘1’–enabled1RWTransmitterHoldingRegisteremptyinterrupt‘0’–disabled‘1’–enabled2RWReceiverLineStatusInterrupt‘0’–disabled‘1’–enabled3RWModemStatusInterrupt‘0’–disabled‘1’–enabled7-4RWReserved.Shouldbelogic‘0’.ResetValue:00hOpenCoresUART16550corespecifications8/11/2002(IIR)TheIIRenablestheprogrammertoretrievewhatisthecurrenthighestprioritypendinginterrupt.Bit0indicatesthataninterruptispendingwhenit’slogic‘0’.Whenit’s‘1’–nointerruptispending.Thefollowingtabledisplaysthelistofpossibleinterruptsalongwiththebitstheyenable,priority,andtheirsourceandresetcontrol.Bit3Bit2Bit1PriorityInterruptTypeInterruptSourceInterruptResetControl0111stReceiverLineStatusParity,OverrunorFramingerrorsorBreakInterruptReadingtheLineStatusRegister0102ndReceiverDataavailableFIFOtriggerlevelreachedFIFOdropsbelowtriggerlevel1102ndTimeoutIndicationThere’satleast1characterintheFIFObutnocharacterhasbeeninputtotheFIFOorreadfromitforthelast4Chartimes.ReadingfromtheFIFO(ReceiverBufferRegister)0013rdTransmitterHoldingRegisteremptyTransmitterHoldingRegisterEmptyWritingtotheTransmitterHo