数字预失真关键技术-ppt3

第三章数字预失真电路设计及实现第章数字预失真电路设计及实现第一节基于FPGA电路的预失真电路设计第节基于FPGA电路的预失真电路设计第二节预失真器参数的实时提取及实现第三节基于ASIC电路的数字预失真器设计及实现1.Intersil数字预失真线性化解决方案介绍数字预失真线性化解决方案介绍2.PMC-Sierra数字预失真线性化解决方案介绍3.TI数字预失真线性化解决方案介绍4Optichron数字预失真线性化解决方案介绍4.Optichron数字预失真线性化解决方案介绍第四节非线性建模及预失真性能快速评估软件介绍DSP模块结构+PipeliningRegistersutMUX+-ΣRegisters„HighPerformanceDSPOperation−18x18Functionsat282MHzOptionalOutputOutpu+-ΣInputR„Input,Output&Pipeliningregisters−ReduceoverallLogicusage„Add/Accumulate/Subtract−Signed&unsignedoperations−DynamicallychangebetweenAdd&Subtract„Supportcomplexmultiplications····-+−(Ar+jAi)x(Br+jBi)=(ArBr–AiBi)+j(AiBr+ArBi)−4Multiplications,1Addition&1Subtraction2数字预失真参考设计I&QdPAI,QoutI,QoutDSPBlocksmodI,QinaddressFIRRAMLUT(∆I&∆Q)I&QDemodr(I2+Q2)1/2∆I=∆r*sin(∆φ)∆Q=∆r*cos(∆φ)RAMI&QDemodr(I2+Q2)1/2·(-1)·(-1)delayCORDICFIRφarctan(I/Q)φarctan(I/Q)delay·(-1)·(-1)SyncNCOProcessor+hardwareacceleration3CORDIC算法•Hardwareefficientalgorithmforcomputingfunctionssuchas:–TrigonometricHyperbolic–Hyperbolic–Logarithmic•Iterativesolutionthatusesonlyshiftsandadding/subtractinggg–Highperformanceasnomultiplicationsanddivisionsdivisions–Simple/lesshardwarerequired4AlteraCORDICDPD解决方案CORDICX_inYinX_outY_inZ_inmodeY_outZ_out•CartesiantoPolarconversion•X_in,Y_in=Cartesianvalues,Z_in=0,mode=0•X_out=magnitude,Z_out=phase•PolartoCartesianconversionXiitdZihYi0d1•X_in=magnitude,Z_in=phase,Y_in=0,mode=1•X_out,Y_out=Cartesianvalues•Modeselectsconversiondirection•Pipelinedenablingnewinputstobeappliedineveryclkcycle•Afterinitiallatencyvalidoutputswillappearoneveryclkcycle•Timesharing:oneachclkcyclethemodeoftheCORDICcanbechanged5CORDIC构架Iteration1IterationnQuadrantdetect&Add/Sub&RegQuadrantAdjustIPmodify&ShiftRegAdjust•ParallelArchitectureenablinghighperformance•CORDICalgorithmcanonlydealwithvectorrotationsof–90to+90degrees•CORDICalgorithmcanonlydealwithvectorrotationsof–90to+90degrees•Requireadditionallogic(Quadrantblocks)tobeabletodealwithvectorsinanyofthefourquadrants•Parameterisablecode•inputvectorwidthsandinputvectorwidthsand•numberofiterationscanbechanged.6CORDIC实现CORDIC实现实实•LEsinAlteraPLDs–EachLEissuitedforimplementingtherequiredadders/subtractors.LEscandynamicallychangefromoperatingasan–LEscandynamicallychangefromoperatingasanaddertosubtractor–EachLEcontainsaregisterg•PerformanceVectorIterationsFmaxLEsrequiredVectorWidthsIterationsFmaxLEsrequiredAbsno.%oftotalin1S10in1S101616219MHz130012%3232189MHz460043%3232189MHz460043%7第三章数字预失真电路设计及实现第章数字预失真电路设计及实现第一节基于FPGA电路的预失真电路设计第节基于FPGA电路的预失真电路设计第二节预失真器参数的实时提取及实现第三节基于ASIC电路的数字预失真器设计及实现1.Intersil数字预失真线性化解决方案介绍数字预失真线性化解决方案介绍2.PMC-Sierra数字预失真线性化解决方案介绍3.TI数字预失真线性化解决方案介绍4Optichron数字预失真线性化解决方案介绍4.Optichron数字预失真线性化解决方案介绍第四节非线性建模及预失真性能快速评估软件介绍8自适应算法实现预失真器参数的提取S2.1)HardCoreAdvantages•HighPerformance922TDMIoneMIPS200g•Time-to-Market•LotsofOn-ChipMemory•LeverageLargeExistingCodee(Dhryst100SoftCoreAdvantages•Flexibility•LowCostBaserformance2050•PortableDesign•Scalability•ObsolescenceProof•FitsBroadRangeofAlteraPLDFamiliesPer200SoftCoreHardCore•FitsBroadRangeofAlteraPLDFamiliesSoftCoreHardCore9基于改进型脉动阵列QR-RLS自适应算法)(),1(),...,1(),(MxMxnxnx−−)1(),2(),...,1(),(−−−MxMxnxnx)1(),2(),...,1(),(xxnxnx−0121,,...,,−−)(),1(),...,1(),(MyMynyny+−10新脉动阵列---三角部分R00R01R11x(2)x(2)/x(2)///P*M-1x(M)x(M-1)x(N)00000N-M+1预加阵列原三角阵列9注意此处是R33R22R02R03R12R13R23x(2)/x(2)/2x(1)x(1)x(2)x(N-M+1)00000//P-1P=3,M=2的特例R55R44R04R05R14R15R24R25R34R35R45x(1)/x(1)/x(1)/x(1)/2(2)(M)(M+1)(N)00000////P-1U0U1U2U3U4U5y(2)y(M)y(M+1)y(N)00000innx,)(innx)(innx)(0)(0)(:,=innx初始化outcinR1:=c初始化RinsRcR****2/1+=λRinsRcRinout***2/1λ−=outnx)(ininoutnxnxnx)(*)()(,=innx)(innx)(:初始化0)(=innxoutsoutRinR00==Rs1:初始化RinsRcR***+=λccout=ssout=22*inRxtemp+=λtempRiinoutMnxnx)()(1=−outMnx)(1−in)(in)(0)(=innx1,..1,0−=Mi001===RscinintempRsin/=tempRc/*2/1λ=tempR=新阵列的三角阵列和功能函数11新脉动阵列-逆向阵列部分W2RUinWout1Wout20210===WoutWoutUin时，RUinWoutWout/21==Wout000UtWiUi时UinWoutUoutWinR000===UoutWinUin时，WinRUinUout*−=WinWout=新阵列的逆向阵列结构图和功能函数12新脉动阵列的记忆项式模型实现UwRwRwRwRwRwR=++++++******三角阵列QR分解所实现的结果nnnnnnUwRwRwRwRUwRwRwRwRwRUwRwRwRwRwRwR=++++=+++++=++++++*...****...****...224243232221141431321211100404303202101000nnnnUwRwRUwRwRwR=++=+++*...**...**4444433434333nnnnUwR=*#逆向阵列实时处理权值的依据11=−−RUwMM0,...3,2)(111,11−−=−=∑+=−−MMkwRURwRnkjjkjkkkkMMM13IAlteraNiosIIDPD参数提取解决方案AlteraNiosIIDPD参数提取解决方案TDUCTDUC--IQToDUCToDUCQTableIQQLUT(I&Q)~100entries12bitWordlengthabeAddressCalc(I2+Q2)1/212bitWordlengthSAdaptiveEst.AlteraMegaCoreIPDelayMatchingCompare&EstimateRSI&QDemodulatorFFTLoopDelayEstimatorEmbeddedProcessor14主要实现部分主要实现部分实实•Forwardpath:I,Qmultipliers•Lookuptable:DualportmemoryLookuptable:Dualportmemory•Feedbackpath–Nioswithcustominstructions–CORDICacceleration–Multiplyacceleration15定制指令实例定制指令实例OptionalFIFO,Memory,OtherLogicALUALU+定实定实NiosProcessorIntegerMult/ExampleALUOnly+IntgrMultALU+CmplxMultIntegerMult/ComplexMultMultLoopTime(us)11.1900.5600.011LoopClocks1119561.1MULClocks2533-x50ComplexMultsperSecond89K1.8M90.9MHardwarex50LoopTime=ExecutionofasinglecomplexmultiplyLoopClocks=NumberofclockstoexecutesingleiterationMULCl