(4)异步FIFO电路设计源代码

FPGA电路设计FIFO源代码`defineADDR_WIDTH8//地址位宽`defineDATA_WIDTH8//数据位宽`defineRAM_WIDTH8//RAM数据位宽`defineRAM_DEPTH256//RAM深度modulefifo_test(clk_100M,//写时钟clk_5M,//读时钟rst_n,//全局复位信号wr_en,//写使能低有效rd_en,//读使能低有效wr_data,//8位数据输入rd_data,//8位数据输出wr_full,//写满标志高有效rd_empty);//读空标志高有效//输入信号inputclk_100M;inputclk_5M;inputrst_n;inputwr_en;inputrd_en;input[`DATA_WIDTH-1:0]wr_data;outputreg[`DATA_WIDTH-1:0]rd_data;outputregwr_full;outputregrd_empty;reg[`RAM_WIDTH-1:0]mem[`RAM_DEPTH-1:0];//8位256单元reg[`ADDR_WIDTH-1:0]wr_addr;//8位写地址reg[`ADDR_WIDTH-1:0]rd_addr;//8读地址regrd_flag;regwr_flag;//写地址产生逻辑always@(posedgeclk_100Mornegedgerst_n)beginif(!rst_n)beginwr_addr=8'h0;wr_flag=0;endelseif(!wr_en)beginif(!wr_full&&(rd_addr!=(wr_addr+1)))beginwr_flag=1;wr_addr=wr_addr+1'b1;endelsewr_flag=0;endend//写数据产生逻辑always@(posedgeclk_100M)beginif(!wr_en&&!wr_full&&wr_flag)mem[wr_addr]=wr_data;end//写满产生标志always@(posedgeclk_100Mornegedgerst_n)beginif(!rst_n)wr_full=0;elseif(rd_addr==(wr_addr+1))wr_full=1'b1;elsewr_full=1'b0;end//读地址产生逻辑always@(posedgeclk_5Mornegedgerst_n)beginif(!rst_n)beginrd_flag=0;rd_addr=8'd0;endelseif(!rd_en)beginif(!rd_empty&&(wr_addr!=(rd_addr+1)))beginrd_flag=1;rd_addr=rd_addr+1'b1;endelserd_flag=0;endend//读数据产生逻辑always@(posedgeclk_5M)beginif(!rd_en&&!rd_empty&&rd_flag)rd_data=mem[rd_addr];end//读空产生标志always@(posedgeclk_5Mornegedgerst_n)beginif(!rst_n)rd_empty=1'b1;elseif((wr_addr==(rd_addr+1))||(wr_addr==rd_addr))rd_empty=1'b1;elserd_empty=1'b0;endendmodule//激励源代码：modulefifo_test_IB;regclk_100M;regclk_5M;regrst_n;//全局复位信号regwr_en;//写使能regrd_en;//读使能reg[`DATA_WIDTH-1:0]wr_data;wire[7:0]rd_data;wirewr_full;wirerd_empty;reg[7:0]cnt;fifo_testfifo1(clk_100M,clk_5M,rst_n,wr_en,rd_en,wr_data,rd_data,wr_full,rd_empty);always#15clk_5M=~clk_5M;//读时钟always#5clk_100M=!clk_100M;//写时钟initialbeginrst_n=0;clk_100M=0;clk_5M=1;wr_en=0;rd_en=0;#25rst_n=1;endalways@(posedgeclk_100Mornegedgerst_n)beginif(!rst_n)wr_data=8'd0;elsewr_data=cnt;endalways@(posedgeclk_100Mornegedgerst_n)beginif(!rst_n)cnt=8'd38;elsecnt=cnt+1'b1;endendmodule