16位流水线ADC系统级建模及仿真-刘蒲霞

　26　12200912MICROELECTRONICS&COMPUTERVol.26　No.12December2009:2008-12-05:(9140A08020507)16ADC刘蒲霞,陆铁军,王宗民(,100076)　:基于MATLAB/Simulink的平台,设计并实现了16bit100M流水线模数转换器(ADC)系统仿真的理想模型.在充分掌握流水线ADC整体结构基础上,对其基本模块进行建模,充分考虑并加入电路的非理想特性和噪声,使整个系统模型接近实际电路.在输入信号为40MHz,采样时钟频率为100MHz时,分别对理想模型和加入非理想因素后的模型进行仿真比较,得到各项性能指标.对实际电路的设计具有一定的借鉴作用.:流水线ADC;MATLAB;非理想特性;系统模型:TN402　　　　　:A　　　　　:1000-7180(2009)12-0120-05SystemModelingandSimulationof16-bitPipelinedADCLIUPu-xia,LUTie-jun,WANGZong-min(BeijingMicroelectronicsTechnologyInstitute,Beijing100076,China)Abstract:ByusingMALAB/Simulink,thesystemlevelmodelingandsimulationofa16bit100MpipelinedADCisde-signedandrealized.BasedonknowingaboutpipelinedADCwell,thebasicmodulesofthesystemaremodeled;mean-whiletheerrorsofrealcircuitsaretakenintoconsideration,sothewholemodelisfullyclosedtotherealsystem.Withtheinputsignalfrequencyof40MHzandsamplingclockof100MHz,simulationresultsofidealmodelarecomparedwithandthatofthenonidealone,thecomparisonresultscangivehelpfulinformationoncircuitsdesigning.Keywords:pipelinedADC;MATLAB;nonidealcharacters;systemmodel1　,,ADC[1].,.,,,,.SIMULINK[2],16100MHzADC,、、、、,,.2　ADC4.5—3.5—3.5—3.5—3,1.,ADC10:clkgen、S/H、timealign、digitalcorrection、4.5bit、33.5bit、3bit,idealDAC.clkgen,D,,100MHz,clk0.5×10-8s;S/H,ADC,;4.5bit3.5bitsubADC,,,,,ADC;3bitflashADC;timealign,D,D,100MHzADC,0.5×10-8s;digitalcorrection,ADC.S/H、subADC、digitalcorrec-tion.1　16ADC3　S/H,,,.、、.,;、、、,.2,S/H.2　3.1　clockjitter,.,.A,fx(t),δ,,x(t+δ)-x(t)≈2πfAcos(2πft)=δddtx(t)[3]3.3　clockjitter3.2　switchnoise,Ron,Cs,,:Sv(f)=4kTRon.:P2T=∫∞04kTRon1+(2πfRonCs)2df=kTCS,k=1.38×10-23J/K,T,T=300K.,,121　12,:16ADC.3.3　opamp[4],,,.,1/f,1/f,,,.Vn=kTCL,CL≈CF(),.,,,,.4,,:Vout=VinCSCF×Af1+Af(1).4　w,:Vo.ideal=Vout(1-e-tτ)(2),τ,1/w.,,:dVo.idealdt=Voutτ×e-tτ(3),t=0,LV=Voutτ,.LVSR,.t=t0,SR,SR=Voutτ×e-t0τ　e-t0τ=SR·τVout(4),t0.,t0.,,t0(IDEAL),SR.,t0Ideal.Ideal.Ideal=Vout×(1-e-t0τ)=Vout-SR·τ(5)t1,,Ideal,:Ideal=SR·t1t1=VoutSR-τ(6),0t1,,;t1,Ideal=Vout-SR·τ.:Vo,real=SR·t,　tt1Vo,real=(Vout-SR·τ)+SR·τ(1-e-t-t1τ)Vo,real=Vout(1-e-t+t0-t1τ),tt1opamp[5]5.,.5　opamp4　subADCsubADCMADC,MDAC,,.3.5bitsubADC,MADC6.3.5bitMADC14,,(n-0.5)bitMADC(2n-2),-13/16,-11/16,-9/16,-7/16,-5/16,-3/16,-1/16,1/16,3/16,5/16,7/16,9/16,11/16,13/16,,.simulink,,[6].,,、(),.,,.7.12220096　3.5bitMADC7　subADCMDAC[7],6,0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100-14/16,-12/16,-10/16,-8/16,-6/16,-4/16,-2/16,0,2/16,4/16,6/16,8/16,10/16,12/16,14/16,,(n-0.5)bitMDAC:VDAC=m+1-2n-12n-1Vref(mMDAC,MADC),,subADC:Vout=(Vin-m+1-2n-12n-1Vref)2n-1simulink.().14O1～O14,D1～D4.:D1=O1O2+O3O4+O5O6+O7O8+O9O10+O10O11+O13O14=(O14+O1)(O2O3)(O4O5)(O6O7)(O8O9)(O10O11)(O12O13)D2=O2O4+O6O8+O10O12+O14=(O12+O2)(O4O6)(O8O10)+O14D3=O4O8+O12D4=O8,subADC,.5　digitalcorrectionADC[8],.ADC,.ADC,,..nADCn+1ADC.0.5..,.,,ADC.6　,,,S/H,0,ADCfft.,δmax=0.1ps,A0=10000,Cs=C0,Cf=Cs,SR=1e8＊8V/sw=1e8＊8rad/s,8.,,,,,.8,,CfCs,Cs=C0,Cf=1.05C0,,9.,,.8,,SR=1e6＊8V/s,,,10.8　7　Simulink,Hspice,,,,123　12,:16ADC,ADC.,.10　9　,:[1],,.CMOS[M].:,2006.[2],,.Matlab7.0/Simulink6.0[M].:,2005.[3],,.ADC[J].,2006,29(4):1288-1291.[4]BehzadRazavi.DesignofanalogCMOSintegratedcircuits[M].NewYork:McGraw-Hill,2003.[5]TingqianChen,BingkunYao,JunXu,etal.Asystematicerrormodelofhigh-resolutionpipelinedanalog-to-digi-talconverters[J].IEEE,2006,2(6/9):158-161.[6]ShaoshiYan,XiTian,XinZhao,etal.Behavioralmodelofdataacquisitionsystembyusingsimulink[C]//7thIn-ternationalConferenceonASIC.Guilin:IEEEInc.,2007:1273-1276.[7],.1250MspsA/D[M].:,2007.[8]FangBing,WangDonghui,ZhangTiejun,etal.Model-ingandsimulationofanopen-looparchitectureADC[C]//7thInternationalConferenceonASIC.Guilin:IEEEInc.,2007:1193-1196.:　,(1984-),.ADC.(上接第119页)[3]ClaudioRMirasso.Chaosshift-keyingencryptioninchaoticexternal-cavitysemiconductorlasersusingasingle-receiverscheme[J].IEEEPhotonicsTechnologyLet-ters,2002,14(4):456-458.[4],,.[J].:,2004,4(1):56-59.[5],,,.[J].,2004,32(7):1131-1134.[6],.[J].,2007,24(3):130-132.:　　,(1981-),.、.　,(1964-),,.、.1242009