SMI传感器AN05-001应用笔记

1、SILICONMICROSTRUCTURESINCORPORATEDAN05-001NotesforDigitalCommunicationwithSM5800SeriesPartsAPPLICATIONNOTE2005SMISiliconMicrostructures,Inc.♦1701McCarthyBlvd.♦Milpitas,CA95035♦USATel:408-577-0100♦Fax:408-577-0123♦Sales@si-micro.com♦(I2C)Businterfaceforalldigitalcommunication.UsingtheI2Cbusthecorrecteddigitalpressureanddigitaltemperaturevaluesareaccessedfromonboardmemoryregisters.DIGITALCOMMUNICATIONBASICSTheI2Cbusinterfaceutilizesatwo-wiremethodforcarryinginformationbackandforthbetweenintegrat。

2、edcircuitdevicesconnectedtothebus.Thetwo-wiremethodiscomprisedofabi-directional,8-bitserialdata(SDA)lineprovidingthepathfordatatransfersandaserialclock(SCL)lineforsynchronizingthedatatransfers.AMasterdeviceintheformofapersonalcomputerormicrocontrollerinitiatesandterminatesdatatransfersontheSDAlineandgeneratestheclocksignalontheSCLline.ASlavedevice(whichrepresentstheSM5800seriesproduct)receivesrequestsfromtheMasterandtransmitsdataaccordingtotherequest.WhenmultipleSlavedevicesareconnectedtothebus,。

3、eachSlavemusthaveauniqueaddressandtheMastermustusethisuniqueaddresswhenperformingdatatransferswithaparticularSlave.AdiagramoftheI2CbuswithaMasterandmultipleSlaves(orSM5800parts)isshowninFigure1.MasterSlave1Slave2Slave3Figure1.MultipleSM5800seriesdevicesconnectedtotheI2CbusDATATRANSFERThedatatransferprocessbeginswiththeMasterissuingaSTART(S)command,whichalertsallSlavedevicesofthependingtransferrequest.TheMasterthenspecifieswhichSlavedevicetocommunicatewithandhowthedatawillflowbetweentheMasterandS。

4、lave.Next,theMasterwaitsfortheaddressedSlavetorespond.WhenthedesiredSlaveresponds,theMasterandSlavebegintheprocessoftransmittingdatabackandforth.ThetransferprocessendswiththeMasterissuingaSTOP(P)command.Figure2providesadiagramshowingasimpledatatransfersequence.START&STOPCONDITIONSInitiatedbytheMaster,aSTARTconditionedisidentifiedbyaHIGHtoLOWtransitionoftheSDAlinewhilemaintainingastableHIGHconditionontheSCLline.AlldatatransfermustbeginwithaSTARTconditionandthebuslinesareconsideredbusyafteraSTARTc。

5、onditionisissued.ToendthetransferofdatatheMasterinitiatesaSTOPcondition,whichisidentifiedbyaLOWtoHIGHtransitionoftheSDAlinewhilemaintainingastableHIGHconditionontheSCLline.AN05-001NotesforDigitalCommunicationwithSM5800SeriesPartsAPPLICATIONNOTE2005SMISiliconMicrostructures,Inc.♦1701McCarthyBlvd.♦Milpitas,CA95035♦USATel:408-577-0100♦Fax:408-577-0123♦Sales@si-micro.com♦(LSB)8SLAVEADDRESS(BEGINSWTHMSB)ACKDATA(BEGINSWTHMSB)PACKSCLSDAHIGHLOWHIGHLOWSTARTCONDITIONSTOPCONDITIONBITSBYTECOMPLETE,CLOCKHEL。

6、DLOWUNITLRECEIVINGDEVICEISREADYFORNEXTOPERATIONFigure2.DiagramofasimpledatatransfersequenceDATAFORMAT&VALIDITYTheSDAlineisan8-bitdigitallineandthisdefinesthesizeofeachbytetransferred.AnacknowledgebitstartswiththeTransmitterreleasingtheSDAlineHIGHatthestartoftheclockcycleimmediatelyfollowingabytetransfer.TheReceivermustthenpulltheSDAlineLOWduringtheHIGHperiodofthesameclockcycle.Theset-upandholdtimesfortheSDAandSCLlinesareprovidedinAPPENDIXA.EverybytetransferredfromTransmittertoReceiverstartswitht。

7、hemostsignificantbit(MSB).ValiddatatransfersonlyoccurduringtheHIGHperiodoftheSCLclock.IfaReceiverneedstimetocarryoutarequestbeforereceivinganotherbyte,itcanholdtheSCLlineLOW.TodothistheReceiverperformsaninternalinterrupttoholdtheSCLLOW,whichforcestheTransmittertowaitbeforesendingthenextbyte.Whenready,theReceiverreleasestheSCLlineanddatatransfercontinues.ADDRESSINGASLAVEDEVICEAllSlavedevicesmusthaveauniqueidentificationoraddress.ASlaveaddresscannotexceedalengthofsevenbits.TheSlaveaddresssharesspa。

8、ceintheaddressbytewitharead/writebitandthemaximumlengthoftheaddressbyteiseightbits.Toconstructtheaddressbyte,placetheSlaveaddressattheMSBoftheaddressbyteandplacetheread/writebitattheleastsignificantbit(LSB).TheaddressbytealwaysfollowsaSTARTcondition.WhenanaddressbyteissentovertheSDAline,eachSlavecomparestheMSBofthisbytewithitsownuniqueaddress.TheSlavewiththematchingaddressbecomesactiveandrespondsbysendinganacknowledgebitalongtheSDAlinetotheMaster.HowtheSlaverespondstothenextbytetransmittedbytheM。

9、asterfollowingtheacknowledgementdependsontheread/writebit.WhentheLSBoftheaddressbyteis“1”theSlavetransmitsdatafortheMastertoread.WhentheLSBoftheaddressbyteis”0”theSlavewaitsfortheMastertowritedatatotheSlave.SILICONMICROSTRUCTURESINCORPORATEDAN05-001NotesforDigitalCommunicationwithSM5800SeriesPartsAPPLICATIONNOTE2005SMISiliconMicrostructures,Inc.。