基于FPGA的数字调制解调器设计

基于FPGA的数字调制解调器设计摘要本设计使用FPGA在EDA技术开发软件QuartusⅡ上实现以正弦信号为载波的三种调制信号ASK、FSK、PSK的调制和解调。系统采用ALTERA公司生产的DE2开发板，CycloneIIEP2C35F672C6型号的FPGA和EPCS16系列的配置驱动，使用VHDL硬件描述语言实现，系统时钟为50MHZ，经四分频产生一路时钟信号经过DDS波形发生器形成ASK，PSK及FSK的一路载波，FSK的另一路载波由系统时钟经八分频后经过DDS波形发生器后产生。由于ASK和PSK调制特性相近，载波都为一路信号。因此在设计时将ASK和PSK调制放在同一模块里设计，用一个选择键和两个基带信号控制端来控制。系统时钟经过512分频后经过随机信号模块产生一路周期为15的伪随机序列作为数字调制的基带信号。在解调时，用非相干解调法解调ASK和PSK信号，用过零检测法解调FSK信号。经过功能仿真和验证后，测试输出信号与基带信号是否相符。关键词：FPGA,ASK,PSK,FSKDigitalmodulationanddemodulationbasedonFPGAAbstractThisdesignusesFPGAonEDAtechnologydevelopmentplatformQuartusⅡtoachievethegenerationandthedemodulationofthreemodulationsignal——ASK,FSK,PSKascarrierthroughsinusoidalsignals.ThesystemusestheALTERAcompany'sDE2developmentboard,FPGAofTypeCycloneIIEP2C35F672C6FPGAanddriverconfigurationofEPCS16series.ThissystemisrealizedinVHDLhardwaredescriptionlanguage,whoseASK,PSKandFSKcarrierisgeneratedwhenthefourfrequencyproducesaclocksignalthroughtheDDSwaveformgenerator,andthesystemclockis50MHZ.BecausethecharacteristicsofASKandPSKmodulationaresimilartoeachother,whichmeanstheircarrierarebothonewaysignal,themodulationofASKandPSKareputonthesamemodelwhendesigned,withaselectionkeyandthetwobasebandsignalcontrolendscontrolling.Systemclockgeneratespseudorandomsequencebasebandsignalswhoseoneroadcycleis15asbasebandsignalsthroughrandomsignalmodelafterthe512frequencydivision.Wheninmodulation,weusenoncoherentdemodulationtodemodulateASKandPSKsignal,andthezerocrossingdetectionmethodforFSKsignaldemodulation.Afterthesystemistestedthroughthefunctionsimulationandverification,whethertheoutputsignalandthebasebandsignalareconformedtoeachotherornotwillbetestedKeywords:FPGA,ASK,PSK,FSK目录1绪论..........................................................11.1课题背景与研究现状.........................................11.1.1数字调制解调背景知识....................................11.1.2FPGA背景知识...........................................21.2课题的主要研究工作.........................................41.3本论文的结构...............................................42.EDA技术简介...................................................62.1QUARTUSII简介..............................................62.1.1QuartusII的使用及主要设计流程.........................72.1.2QuartusII的原理图输入设计流程........................102.1.2SignalTapII逻辑分析仪的使用..........................112.2VHDL语言简介..............................................132.2.1VHDL的基本结构........................................142.2.2VHDL的基本语法........................................193.数字调制解调原理.............................................213.1ASK的调制与解调...........................................213.1.1ASK调制原理...........................................213.1.2ASK解调原理...........................................233.2PSK的调制与解调...........................................233.2.1PSK调制原理...........................................233.2.2PSK解调原理...........................................253.3FSK的调制与解调...........................................263.3.1FSK调制原理...........................................263.3.2FSK解调原理...........................................284硬件模块方案设计与实现........................................304.1DDS（直接数字式频率合成器）...............................304.1.1DDS原理...............................................304.1.2硬件模块设计图.........................................314.1.3频率控制模块..........................................324.1.4波形选择模块..........................................324.1.5波形存储模块..........................................334.1.6顶层实体模块..........................................334.1.7程序及仿真结果分析....................................344.2M序列发生器...............................................354.2.1m序列原理.............................................354.2.2m序列发生器设计.......................................374.2.3m序列产生模块.........................................404.2.4m序列仿真结果分析.....................................404.3分频器设计................................................414.4ASK/PSK调制与解调.........................................424.4.1ASK/PSK调制方案.......................................424.4.2ASK/PSK调制模块.......................................434.4.3ASK/PSK调制仿真结果分析...............................434.4.4ASK/PSK解调方案.......................................444.4.5ASK/PSK解调模块.......................................454.4.6ASK/PSK解调仿真结果分析...............................464.5FSK调制与解调.............................................474.5.1FSK调制方案...........................................474.5.2FSK调制模块...........................................484.5.3FSK仿真结果分析.......................................484.5.4FSK解调方案...........................................494.5.5FSK解调模块...........................................504.5.6FSK解调仿真结果分析...................................505系统调试.....................................................515.1系统电路图...............................................515.2系统仿真结果.............................................51结论...........................................................54致谢...........................................................55参考文献.......................................................56附录：源代码..........