Cortex-M-portfolio

CONFIDENTIAL1ARM®Cortex®-MProcessorPortfolioQ1’2014EmbeddedCPUTeamCONFIDENTIAL2AgendaOverviewMarketchallengesIntroducingthefamilyCommontechnologybenefitsSpanningtheapplicationsFundamentaltechnologiesProcessorcoreThumb®-2instructionsetNVICWICCoreSight™EcosystemandCMSISTheARMCortex®-MprocessorsCortex-M0Cortex-M0+Cortex-M1Cortex-M3Cortex-M4DevelopmenttoolsandecosystemSummaryCONFIDENTIAL3MobilecomputingandGatewaysCellularmodems,SBCsARMCortex-R&Cortex-ASensornodesMCUs,sensors,IoTARMCortex-MInfrastructureServers,networkinfrastructureARMCortex-AARM®Cortex®ProcessorapplicationsCONFIDENTIAL4ARM®Cortex®-MProcessorsolutionEnergyefficiencyLowerenergycostsEaseofuseLowersoftwarecostsHighperformanceCompetitiveproductsReducedsystemcostLowersiliconcostsLowpowerimplementationSleepmodesupportWake-upInterruptControllerIncreasedintelligenceatnodeBroadtoolsandOSsupportBinarycompatibleroadmapCMSISsupportPureCtarget32-bitRISCarchitectureHighefficiencyprocessorcoresIntegratedInterruptController(NVIC)‏Thumb®-2codedensityAreaoptimiseddesignsCoreSight™supportCONFIDENTIAL5Cortex-MConfigurableLowSiliconAreaEaseofUseDeterministicWIDELYADOPTEDMARKETPROVENHIGHVOLUMEEnergyEfficientCortex-M0“8/16-bit”applicationsLowestcostCortex-M4“32-bit/DSC”applicationsMCUplusDSPAcceleratedSIMD,FP&SPCortex-M3“16/32-bit”applicationsPerformanceefficiencyFeaturerichconnectivityCortex-M0+“8/16-bit”applicationsLowestpowerOutstandingEnergyefficiencyARM®Cortex®ProcessorfamilyCONFIDENTIAL6ARM®Cortex®-MProcessors–provensuccessIRFireDetectorsIntelligentVendingTele-parkingEnergyEfficientAppliancesUtilityMetersExerciseMachinesIntelligenttoys212+licenseesofCortex-MprocessorsOver3,000Cortex-MbasedMCUtypesTensofthousandsCortex-MbasedapplicationsWearablesCONFIDENTIAL7ARM®Cortex®-MSustainedgrowthTotalembeddedprocessorvolume2012=2.2Bn2013=2.9Bn18+partnersinfullproductionWidelyusedinallmarkets:AutomotiveConsumerGaming&ToysIndustrialInternetofThings0306090120150180210240270Q12009Q2Q3Q4Q12010Q2Q3Q4Q12011Q2Q3Q4Q12012Q2Q3Q4Q12013Q2Q3TotalCortex-MMCUShipments(MillionUnitsperQuarter)MeteringSecurityTelecomWearableWhiteGoodsCONFIDENTIAL8ThelargestopenmarketMCUproductportfolio(101)(385)(568)(89)(43)(7)(9)(955)(59)(43)(18)(241)(111)(243)(3)ListedpartsonpartnerswebasofendofSeptember2013Choosefrommorethan3.000cataloguepartsCONFIDENTIAL9FundamentalTechnologiesCONFIDENTIAL10Instructionsetarchitecture(ISA)Thumb™32-bitoperationsin16-bitinstructionsIntroducedinARM7TDMI®processor(‘T’standsforThumb)SubsequentlysupportedineveryARMprocessordevelopedsinceThumb™-2Enablesaperformanceoptimisedblendof16/32-bitinstructionsAllprocessoroperationscanallbehandledin‘Thumb’stateSupportedacrosstheCortex®-MprocessorrangeThumbARM7™ARM9™Cortex-A9Cortex-R4Cortex-M3Cortex-M0+Cortex-M4Cortex-M0ThumbinstructionsetupwardscompatibilityCONFIDENTIAL11PowerfulandscalableISAFloatingPointGeneraldataprocessingI/OcontroltasksAdvanceddataprocessingBitfieldmanipulationsDSP(SIMD,fastMAC)ARMv6-MARMv7-MARMv7E-MCONFIDENTIAL12LinearsetofprogramregistersAllregistersare32-bitwide13generalpurposeregistersOnly3specialregistersProgramStatusRegisterr0r1r2r3r4r5r6r7r8r9r10r11r12r15(PC)r14(LR)PSRr13(SP)CONFIDENTIAL134GBlinearmemoryspaceAlllocationsalwaysaccessiblebytheSWOptionalmemoryprotectionunitStandardacrossallCortex®-MimplementationsPredefinedmemorymap0x000000000xFFFFFFFFCODEregionSRAMregion0x200000000x40000000PeripheralregionRAMregionDeviceregion0x600000000xA0000000Systemregion0xE0000000ProgramflashSRAMPeripheralsOffchipmemoryOffchipperipheralsSystemcomponentsanddebugCONFIDENTIAL14Memoryprotectionunit(MPU)PreventsapplicationtaskfromcorruptingOSorothertaskdataImprovessystemreliabilityUptoeightconfigurableregionsAddressSizeMemoryattributesAccesspermissionsOptionalinallprocessors(exceptCortex-M0andM1)ARM®Cortex®-MMEMORYdatafortaskAdatafortaskCdataforOSkerneldatafortaskBI/O#2I/O#1I/O#0I/O#nMPUMPUconfigurationOSkernel(privileged)taskAtaskBtaskCCONFIDENTIAL15Nestedvectoredinterruptcontroller(NVIC)FasterinterruptresponseWithlesssoftwareeffortVariousoptimizations(e.g.tail-chain)ISRwrittendirectlyinCInterrupttableissimplyasetofpointerstoCroutinesISRsarestandardCfunctionsIntegratedNVIChandlesSavingregistersExceptionprioritizationExceptionnesting8051Cortex-M1.SJMP/LJMPfromvectortabletohandler2.PUSHPSW3.ORLPSW,#00001000b(toswitchregisterbank)4.Startingrealhandlercode1.StartingrealhandlercodeTail-chainCONFIDENTIAL16CodedensityCortex-Mshowssmallercodesizethan8/16-bitdevicesBestin-classcodedensity,reducingflashsizeandpowerconsumptionReachsmallestformfactorandcostSensorsMobileequipmentMedical4.8966.44610.20610.066024681012Cortex-MABCCoreMarkCodeinkBCSP16(2x2mm)QFN20(3x3mm)CoreMarkcodecompiledoptimizedforsizeCONFIDENTIAL17NormalizedcodesizeusingpublicbenchmarkdataCodedensityacrossapplications02468101214ABCDCortex®-MCONFIDENTIAL18ARM®Cortex®-MProcessorlowpowertechnologiesIntegratedarchitecturalclockgatingEnabledesignerstoimplementlowpoweroptimizationeasily“Sleep