西工大数字集成电路实验四、译码器的设计及延迟估算

数字集成电路实验报告西北工业大学2014年5月21日星期三实验四、译码器的设计及延迟估算1、设计译码器并估算延迟设计一个用于16bit寄存器堆的译码器，每一个寄存器有32bit的宽度，每个bit的寄存器单元形成的负载可以等效为3个单位化的晶体管(后面提到负载都为单位化后的负载)。提示：可以首先假定每一级的逻辑努力为1，考虑到存在四输入的与非门也可考虑假设总的逻辑努力为2，从而确定译码器的级数。译码器的结构可参考典型的4-16译码器Decoder16outputs32-bitregister①假定4个寄存器地址位的正反8个输入信号，每个信号的输入负载可以等效为10。确定译码器的级数，并计算相关逻辑努力，以此来确定每一级中晶体管的尺寸（相当于多少个单位化的晶体管）及整个译码电路的延迟(以单位反相器的延迟的本征延迟Tp0为单位)。答：9.696/10F96332,10intextgCCC,假定每一级的逻辑努力：G=1，又因为分支努力(每个信号连接8个与非门)：81*8*1B，路径努力8.7686.91GFBH所以，使用最优锥形系数就可得到最佳的电路级数39.36.3ln8.76ln6.3lnlnHN,故N取3级。因为逻辑努力：2121G；路径努力：6.15386.92GFBH则使得路径延时最小的门努力36.5)6.153(3/1NHh。所以：第一级晶体管尺寸为10；故第二级晶体管尺寸为7.681036.5；第三级尺寸为956.1768.27.6；故延迟为：0008.22)36.5136.5436.51(ppptttA1A2A3A4...1096...96!A1!A2!A3!A4②如果在四个寄存器地址输入的时候，只有正信号，反信号必须从正信号来获得。每个正信号的输入的等效负载为20,使用与①中同样的译码结构，在这种条件下确定晶体管的大小并评估延迟(以单位反相器的延迟的本征延迟Tp0为单位)。答：因为输入时通过两级反相器，使这两个反相器分摊原来单个反相器的等效扇出，将两级反相器等效为一级，故其逻辑努力32.236.5h,故36.5,68.2,32.2,32.24321ffff所以：第一级尺寸为：8.5832.220第二级尺寸为：456.1332.28.5第三级尺寸为：36.0620868.2456.13第四级尺寸为：65.9636.503.18正信号通路的延迟为：0036.2236.5136.5436.5132.2132.2pppttt反信号通路情况与上问相同，延迟为0008.22)36.5136.5436.51(ppptttsA1A2A3A4...2096...96译码器和寄存器堆的连接情况(Output输出为1的一行寄存器被选中)2、根据单位反相器(NMOS:W=0.5uL=0.5uPMOS:W=1.8uL=0.5u)，设计出实际电路，并仿真1题中第一问的路径延迟。仿真结果如下：手工测量结果为：tp=9.4413E-08为了简单起见，所有晶体管采用最小尺寸代码如下：.TITLEEXERCISE4CMOSINVERTER(Thefirst).optionsprobe.optionstnom=25.optionspostacctprobeaccurate.optionsingold=2limpts=30000method=gear*ingold：输出数据格式limpts：AC分析中设置总点数method：算法.optionslvltime=2imax=20gmindc=1.0e-12*lvltime:选择时间步长算法imax：最大时间步长gmindc：DC分析时用到的与PN结并联的电导.protect.lib'C:\Eric\DigitalIntegratedCircuit\experiment3\cmos25_level49.lib'TT.unprotect.TRAN200P60NMNMOS_10N_18N_15N_17N_17NMOSW=0.5uL=0.5uMNMOS_11Y10N_5N_18N_18NMOSW=0.5uL=0.5uMNMOS_12N_16N_2GndGndNMOSW=0.5uL=0.5uMNMOS_13N_21N_8N_20N_20NMOSW=0.5uL=0.5uMNMOS_14N_22N_15N_21N_21NMOSW=0.5uL=0.5uMNMOS_15Y11N_10N_22N_22NMOSW=0.5uL=0.5uMNMOS_16N_20N_2GndGndNMOSW=0.5uL=0.5uMNMOS_17N_26N_24N_25N_25NMOSW=0.5uL=0.5uMNMOS_18N_27N_7N_26N_26NMOSW=0.5uL=0.5uMNMOS_19Y12N_5N_27N_27NMOSW=0.5uL=0.5uMNMOS_20N_25N_2GndGndNMOSW=0.5uL=0.5uMNMOS_21N_30N_10N_29N_29NMOSW=0.5uL=0.5uMNMOS_22N_31N_24N_30N_30NMOSW=0.5uL=0.5uMNMOS_23Y13N_7N_31N_31NMOSW=0.5uL=0.5uMNMOS_24N_29N_2GndGndNMOSW=0.5uL=0.5uMNMOS_25N_34N_15N_33N_33NMOSW=0.5uL=0.5uMNMOS_26N_35N_24N_34N_34NMOSW=0.5uL=0.5uMNMOS_27Y14N_5N_35N_35NMOSW=0.5uL=0.5uMNMOS_28N_33N_2GndGndNMOSW=0.5uL=0.5uMNMOS_29N_38N_10N_37N_37NMOSW=0.5uL=0.5uMNMOS_30N_39N_15N_38N_38NMOSW=0.5uL=0.5uMNMOS_31Y15N_2N_39N_39NMOSW=0.5uL=0.5uMNMOS_32N_37N_24GndGndNMOSW=0.5uL=0.5uMNMOS_33N_15N_7GndGndNMOSW=0.5uL=0.5uMNMOS_34N_24N_8GndGndNMOSW=0.5uL=0.5uMNMOS_35N_5A0GndGndNMOSW=0.5uL=0.5uMNMOS_36N_10N_5GndGndNMOSW=0.5uL=0.5uMNMOS_37N_7A1GndGndNMOSW=0.5uL=0.5uMNMOS_38N_8A2GndGndNMOSW=0.5uL=0.5uMNMOS_39N_44A3N_43N_43NMOSW=0.5uL=0.5uMNMOS_40N_43N_47N_46N_46NMOSW=0.5uL=0.5uMNMOS_41N_46N_48GndGndNMOSW=0.5uL=0.5uMNMOS_42N_47GndGndGndNMOSW=0.5uL=0.5uMNMOS_43N_48GndGndGndNMOSW=0.5uL=0.5uMNMOS_44N_2N_44GndGndNMOSW=0.5uL=0.5uMNMOS_1N_1N_2GndGndNMOSW=0.5uL=0.5uMNMOS_2Y8N_5N_3N_3NMOSW=0.5uL=0.5uMNMOS_3N_3N_7N_6N_6NMOSW=0.5uL=0.5uMNMOS_4N_6N_8N_1N_1NMOSW=0.5uL=0.5uMNMOS_5N_12N_8N_11N_11NMOSW=0.5uL=0.5uMNMOS_6N_13N_7N_12N_12NMOSW=0.5uL=0.5uMNMOS_7Y9N_10N_13N_13NMOSW=0.5uL=0.5uMNMOS_8N_11N_2GndGndNMOSW=0.5uL=0.5uMNMOS_9N_17N_8N_16N_16NMOSW=0.5uL=0.5uMNMOS_80N_70N_36N_69N_69NMOSW=0.5uL=0.5uMNMOS_81Y0N_42N_70N_70NMOSW=0.5uL=0.5uMNMOS_82N_68N_40GndGndNMOSW=0.5uL=0.5uMNMOS_83N_71N_40GndGndNMOSW=0.5uL=0.5uMNMOS_84Y2N_42N_72N_72NMOSW=0.5uL=0.5uMNMOS_85N_72N_52N_73N_73NMOSW=0.5uL=0.5uMNMOS_86N_73N_32N_71N_71NMOSW=0.5uL=0.5uMNMOS_87N_67N_40GndGndNMOSW=0.5uL=0.5uMNMOS_88Y1N_41N_66N_66NMOSW=0.5uL=0.5uMNMOS_45N_23N_9GndGndNMOSW=0.5uL=0.5uMNMOS_46N_28N_19N_23N_23NMOSW=0.5uL=0.5uMNMOS_47N_14VddN_28N_28NMOSW=0.5uL=0.5uMNMOS_48N_32A2GndGndNMOSW=0.5uL=0.5uMNMOS_49N_36A1GndGndNMOSW=0.5uL=0.5uMNMOS_50N_40N_14GndGndNMOSW=0.5uL=0.5uMNMOS_51N_9GndGndGndNMOSW=0.5uL=0.5uMNMOS_52N_19A3GndGndNMOSW=0.5uL=0.5uMNMOS_53N_41N_42GndGndNMOSW=0.5uL=0.5uMNMOS_54N_45N_49GndGndNMOSW=0.5uL=0.5uMNMOS_55Y7N_40N_50N_50NMOSW=0.5uL=0.5uMNMOS_56N_50N_52N_51N_51NMOSW=0.5uL=0.5uMNMOS_57N_51N_41N_45N_45NMOSW=0.5uL=0.5uMNMOS_58N_42A0GndGndNMOSW=0.5uL=0.5uMNMOS_59N_49N_32GndGndNMOSW=0.5uL=0.5uMNMOS_60N_52N_36GndGndNMOSW=0.5uL=0.5uMNMOS_61N_53N_40GndGndNMOSW=0.5uL=0.5uMNMOS_62Y4N_42N_54N_54NMOSW=0.5uL=0.5uMNMOS_63N_54N_36N_55N_55NMOSW=0.5uL=0.5uMNMOS_64N_55N_49N_53N_53NMOSW=0.5uL=0.5uMNMOS_65N_56N_40GndGndNMOSW=0.5uL=0.5uMNMOS_66Y3N_41N_57N_57NMOSW=0.5uL=0.5uMNMOS_67N_57N_52N_58N_58NMOSW=0.5uL=0.5uMNMOS_68N_58N_32N_56N_56NMOSW=0.5uL=0.5uMNMOS_69N_59N_40GndGndNMOSW=0.5uL=0.5uMNMOS_70Y6N_42N_60N_60NMOSW=0.5uL=0.5uMNMOS_71N_60N_49N_61N_61NMOSW=0.5uL=0.5uMNMOS_72N_61N_52N_59N_59NMOSW=0.5uL=0.5uMNMOS_73N_62N_40GndGndNMOSW=0.5uL=0.5uMNMOS_74Y5N_36N_63N_63NMOSW=0.5uL=0.5uMNMOS_75N_63N_49N_64N_64NMOSW=0.5uL=0.5uMNMOS_76N_64N_41N_62N_62NMOSW=0.5uL=0.5uMNMOS_77N_66N_36N_65N_65NMOSW=0.5uL=0.5uMNMOS_78N_65N_32N_67N_67NMOSW=0.5